• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집A
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• pp.286-291
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• 2001

Applications of bonded dissimilar materials such as IC package, ceramic/metal and resin/metal bonded joints, are very increasing in various industry fields. It is very important to analyze the thermal stress and stress singularity at interface edges in bonded joints of dissimilar materials. In orer to understand the package crack emanating from the edge of Die pad and Resin, fracture mechanics of bonded dissimilar materials and material properties are obtained. In this paper, the thermal stress and its singularity index for the IC package were analyzed using 2-dimensional elastic boundary element method. Crack propagation angle and path by thermal stress were numerically simulated with boundary element method.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.21-30
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• 2002

According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

• 한국자동차공학회논문집
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• 제16권3호
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• pp.15-22
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• 2008

Applications of bonded dissimilar materials such as integrated circuit(IC) packages, ceramics/metal and resin/metal bonded joints, are very increasing in various industry fields. It is very important to analyze the thermal stress and stress singularity at interface edge in bonded joints of dissimilar materials. In order to investigate the IC package crack propagating from the edge of die pad and resin, the fracture parameters of bonded dissimilar materials and material properties are obtained. In this paper, the thermal stress and its singularity index for the IC package were analyzed using 2-dimensional elastic boundary element method(BEM). From these results, crack propagation direction and path by thermal stress in the IC package were numerically simulated with boundary element method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.321-324
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• 2004

This paper presents a package IC containing some components of DC/DC converter block for mobile phone's sub OLED(Organic Light Emitting Display). Package IC contains a load switch, a control IC, a diode, a switch for on/off operation, and a switch for changing output voltage. It operates with switching frequency of 100kHz, within the range of input voltage, $3.2V\~5.5V$. Duty ratio can be changed up to $93\%$, and maximum power efficiency is $85\%$. This package IC is loaded onto three model of 1.2W mobile phone's sub-OLED.

• 융합신호처리학회논문지
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• 제25권1호
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• pp.46-51
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• 2024

드론은 최초 군사용으로 사용되었으나 최근들어 사용범위가 확대됨에 따라 농업, 서비스, 물류, 레져용 등 다양한 산업분야에서 폭넓게 사용되어지고 있는 추세이다. 리튬폴리머 배터리는 경량이면서 효율이 우수하여 드론의 전원공급 장치로 주로 사용되고 있다. 이에따라 드론에 안정적인 전원공급을 위하여 경량이면서 에너지 밀도가 높은 리튬폴리머 배터리의 필요성이 커지게 되었다. 그러나 리튬폴리머 배터리는 과충전, 과방전, 단락 등의 이유로 발화 및 폭발로 이어질 수 있어 반드시 보호회로를 탑제하여 사용해야한다. 보호회로는 리튬폴리머 배터리의 전압을 모니터링하는 제어IC인 보호 IC와 과방전시 스위치 역할을 하는 듀얼 N-channel MOSFET 등으로 구성되어있다. 따라서 본 논문은 배터리 보호 IC와 스위치 역학을 하는 MOSFET의 반도체 Die Chip을 이용하여 원칩 패키지 IC형태로 구현하였다. 원칩 패키지 IC로 구현하면 기존 부품 대비 최소 67%의 절감효과를 갖게된다.

• 정보처리학회논문지B
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• 제9B권2호
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• pp.245-254
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• 2002

머신비전을 이용한 IC 패키지 마킹검사 시스템은 입력영상으로부터 검사할 요소들의 위치를 식별하고, 추출된 요소들을 학습된 표준 패턴과 비교하여 마킹의 불량 여부를 판단한다. 본 논문에서는 검사 대상 IC 패키지의 위치 판별, 마킹문자 추출, 핀원딤플 검출과 같은 일련의 작업들에 적합한 적응적 다단계 이진화 방법과 마킹문자의 국소적인 오류검출은 물론 잡영에 강건한 정합단위의 동적 선택 방법을 제안한다. 제안하는 이진화 방법은 이진화 대상 영역과 명도 값의 범위를 제한하여 Otsu의 이진화 알고리즘을 적용함으로써 특정 응용에 적응적인 이진화가 가능하다. 정합단위의 동적 선택 방법은 문자추출 및 배치분석에 대한 결과에 따라 정합단위를 선택한다. 그러므로 문자추출 및 배치분석 과정에서 발생하는 예기치 못한 부적절한 상황에서도 가능한 범위내에서 최소의 정합단위를 선택할 수 있다. 제안된 방법을 구현하여 8종의 IC 패키지, 총 280개의 영상에 대하여 실험한 결과, IC 패키지와 핀원딤플의 검출율은 100%였으며, 마킹상태에 대한 판정은 98.8%의 정확도를 나타내어 제안된 방법이 효과적임을 확인할 수 있었다.

• E2M - 전기 전자와 첨단 소재
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• 제10권6호
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• pp.519-527
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• 1997

The micro crack was occurred where the stress concentrated by the thermal stress which was induced during the cooling period after molding process or by the various reliability tests. In order to estimate the possibility of development from inside micro crack to outside fracture, the fracture toughness of EMC should be measured under the various applicable condition. But study was conducted very rarely for the above area. In order to provide a was to decide the fracture resistance of EMC (Epoxy Molding Compound) of plastic package which is produced by using transfer molding method, measuring fracture is studied. The specimens were made with various EMC material. The diverse combination of test conditions, such as different temperature, temperature /humidity conditions, different filler shapes, and post cure treatment, were tried to examine the effects of environmental condition on the fracture toughness. This study proposed a way which could improve the reliability of LOC(Lead On Chip) type package by comparing the measured $J_{IC}$ of EMC and the calculated J-integral value from FEM(Finite Element Method). The measured $K_{IC}$ value of EMC above glass transition temperature dropped sharply as the temperature increased. The $K_{IC}$ was observed to be higher before the post cure treatment than after the post cure treatment. The change of $J_{IC}$ was significant by time change. J-integral was calculated to have maximum value the angle of the direction of fracture at the lead tip was 0 degree in SOJ package and -30 degree in TSOP package. The results FEM simulation were well agreed with the results of measurement within 5% tolerance. The package crack was proved to be affected more by the structure than by the composing material of package. The structure and the composing material are the variables to reduce the package crack.ack.

• 한국공작기계학회논문집
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• 제17권3호
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).

• 센서학회지
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• 제31권1호
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• pp.36-40
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• 2022

High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.