• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.23-29
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• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.39-45
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• 2012

Three-dimensional integrated circuit(3D IC) technology has become increasingly important due to the demand for high system performance and functionality. In this work, BOE and HF wet etching of Cu line surfaces after CMP were conducted for Cu-Cu pattern direct bonding. Step height of Cu and $SiO_2$ as well as Cu dishing after Cu CMP were analyzed by the 3D-Profiler. Step height increased and Cu dishing decreased with increasing BOE and HF wet etching times. XPS analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE and HF wet etching treatment. BOE treatment showed not only the effective $SiO_2$ etching but also reduced dishing and Cu surface oxide rather than HF treatment, which can be used as an meaningful process data for reliable Cu-Cu pattern bonding characteristics.

• Journal of the Microelectronics and Packaging Society
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• v.4 no.1
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• pp.1-12
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• 1997

본 연구에서는 용액성장법에 의해 양자 입자로 구성된 CdS 박막을 슬라이드 유리기 판위에 성장시키고 이들의 구조적 광학적 특성에 대하여 연구하였고 이들 결과를 토대로 용 액성장법으로 성장된 CdS 박막의 양자 사이즈 효과에 대하여 연구하였다. 성장시간은 1, 3, 10, 20분이었고 성장온도는 75$^{\circ}C$였다. X-선 회절 분석결과 본 연구에서 합성된 CdS 박막은 hexagonal상의 결정구조를 갖는 것으로 나타났고 성장시간에 따라 막의 투께는 61~195nm, 입자사이즈는 8.5~22.5nm로 나타났다. 광에너지 변화에 따른 투과도 측정결과 본 연구의 CdS 시료는 성장시간에 따라 에너지 밴드갭이 2.43~2.51 eV로 나타나서 벌크 CdS의 에너 지 밴드갭인 2.42 ev보다 높은 에너지 밴드갭을 갖게 되어 양자 사이즈 효과에 의한 blue shift 현상이 용액성장법에 의해 합성된 CdS 시료에도 존재한다는 것이 밝혀졌다 그리고 이 같은 용액성장법으로 성장된 CdS에 대해 최초로 수행된 Raman 산란 실험결과 이성장방법 으로 성장된 CdS에는 1TO, E2, 1LO 포논 모드가 존재함을 알수 있었고 또한 입자 사이즈 감소에 의한 1LO포논 모드의저주파수 shift 현상 즉 포논 모드의 softening 현상이 있음이 밝혀졌고 softening은 최대6.2%까지 발생하였다. 이와같은 높은 softening은 본연구의 CdS 박막 내 양자 입자의 입도가 작은것에 기인하는 것으로 밝혀졌다. 또한 본 CdS 시료의 양 자 사이즈 효과의 결과로 1TO 포논도 나타났는데 이 1TO 포논과 E2 포논의 Raman shift 는 성장시간 즉 막의 두께와는 무관한 것으로 나타났다.행렬모형(二重比例行列模型)을 이용하여, 산업구조의 변화로 인한 직업별 인력수요 변화가 충분히 고려되도록 하였다. 전망의 결과에 따르면 향후 우리 경제는 지식기반경제(knowledge-based economy)로 이행하고 있다고 볼 수 있다. 우선 산업구조면에서 지식집약적산업으로의 구조조정이 일어나게 되고 이에 따라 산업별 취업구조에서도 고기술산업의 취업준비중이 급속히 증가하게 된다. 직업별 취업분포에 있어서도 전문기술직 행정관리직 등의 고숙련 사무직의 비중은 크게 증가하는 반면 생산관련직과 농림어업직의 비중은 감소하게 된다. 이처럼 경제가 지식집약화되어 감에 따라 고학력자에 대한 수요는 지속적으로 증가하지만 현재 적절한 인력양성과 공급이 이루어지지 않고 있어 향후 기술이나 기능에 따른 수급부일정(需給不一政)(skill mismatch)현상이 매우 심해질 것으로 보인다. 따라서 앞으로의 인력정책에서 가장 주안점을 두어야 할 부분은 첨단기술산업과 관련된 인력의 양성에 있다고 하겠다.2시간까지 LPDG용액은 MEC용액보다 비교적 나은 회복을 보였고 재관류 3일과 7일의 폐기능 평가에서 두 용액 모두에서 폐기능의 점차적 소실을 보였으며 이는 병리조직검사에서 보듯이 폐혐에 의한 외적인 요소라고 생각되며 따라서 LPDG용액은 허혈재관류손상 방지 및 급성폐렴 등 염증을 잘 관리한다면 20시간 이상 LPDG용액의 안전한 폐보존의 가능성 을 얻을 수 있었다.ic 형태로 외래유전자가 발현되었지만 대조구에서 87.0% (26/30개) 배반포기가 $\beta$-Gal 활력을 보인 반면, G418 처리구에서는 모든 배반포기가 $\beta$-Gal 활력을 보였다 (P<0.05). 그러나 대조구 및 G418 처리구의 ICM

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.31-37
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• 2009

Cu-Cu thermo-compression bonding process was successfully developed as functions of the $N_2+H_2$ forming gas annealing conditions before and after bonding step in order to find the low temperature bonding conditions of 3-D integrated technology where the quantitative interfacial adhesion energy was measured by 4-point bending test. While the pre-annealing with $N_2+H_2$ gas below $200^{\circ}C$ is not effective to improve the interfacial adhesion energy at bonding temperature of $300^{\circ}C$, the interfacial adhesion energy increased over 3 times due to post-annealing over $250^{\circ}C$ after bonding at $300^{\circ}C$, which is ascribed to the effective removal of native surface oxide after post-annealing treatment.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.3
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• pp.24-37
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• 2024

Due to the thin nature of semiconductor packages, even minor thermal loads can cause significant warpage, impacting product reliability through issues like delamination or cracking. The mold curing process, which encloses the package to protect the semiconductor chip, is particularly challenging to predict due to the complex thermal, chemical, and mechanical interactions. This study proposes a cost-effective machine learning model to predict warpage in the mold curing process. We developed methods to characterize the curing degree based on time and temperature and quantify the material's mechanical properties accordingly. A Finite Element Method (FEM) simulation model was created by integrating these properties into ABAQUS UMAT to predict warpage for various design factors. Additionally, a Warpage formula was developed to estimate local warpage based on the package's stacking structure. This formula combines bending theory with thermo-chemical-mechanical properties and was validated through FEM simulation results. The study presents a method to construct a machine learning model for warpage prediction using this formula and proposes a cost-effective approach for building a training dataset by analyzing input variables and design factors. This methodology achieves over 98% prediction accuracy and reduces simulation time by 96.5%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Journal of Computational Design and Engineering
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• v.3 no.3
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• pp.198-214
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• 2016

Oval substrates are widely used in automobiles to reduce the exhaust emissions in Diesel oxidation Catalyst of CI engine. Because of constraints in space and packaging Oval substrate is preferred rather than round substrate. Obtaining the flow uniformity is very challenging in oval substrate comparing with round substrate. In this present work attempts are made to optimize the inlet cone design to achieve the optimal flow uniformity with the help of CATIA V5 which is 3D design tool and CFX which is 3D CFD tool. Initially length of inlet cone and mass flow rate of exhaust stream are analysed to understand the effects of flow uniformity and pressure drop. Then short straight cones and angled cones are designed. Angled cones have been designed by two methodologies. First methodology is rotating flow inlet plane along the substrate in shorter or longer axis. Second method is shifting the flow inlet plane along the longer axis. Large improvement in flow uniformity is observed when the flow inlet plane is shifted along the direction of longer axis by 10, 20 and 30 mm away from geometrical centre. When the inlet plane is rotated again based on 30 mm shifted geometry, significant improvement at rotation angle of $20^{\circ}$ is observed. The flow uniformity is optimum when second shift is performed based on second rotation. This present work shows that for an oval substrate flow, uniformity index can be optimized when inlet cone is angled by rotation of flow inlet plane along axis of substrate.

• Journal of the Korean Vacuum Society
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• v.16 no.1
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• pp.74-78
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• 2007

Much interests has been drawn for noble micro-engineering processes for the continuous size reduction on bulk materials from the field of micro-electronics with much downsized IC chips. A traditional microprocessing based on mechanical blade as well as a relatively long pulsed laser usually influence the physico-chemical properties of intact materials when the techniques are applied to process materials with a spatial resolution less than 10 microns. Meanwhile, ultrafast laser pulses are known to exhibit a very small heat-affect zone(HAE) compared to the traditional laser processing and to be applicable for the new functional materials with high performance in optical and electrical properties. In this report, we will review in brief the recent research works on the enhancement of micro-cutting speed of thin silicon wafer as well as the formation of Ge nanostructures based on ultrafast laser pulses.