• Korean Journal of Veterinary Research
• /
• v.45 no.2
• /
• pp.191-197
• /
• 2005

An immunochromatographic (IC) strip for the rapid detection of Salmonella spp. in the enriched sample was developed. Affinity purified Salmonella polyclonal antibody was conjugated with 40 nm colloidal gold particles which were prepared by citrate method in our laboratory. The antigen-antibody-gold complex was captured by Salmonella antibody attached to test line of nitrocellulose membrane during the capillary migration of sample. Specificity of the IC strip was calculated to be 100% (12/12) and sensitivity was 97.6% (41/42) in the test with pure cultured bacteria. Salmonella was artificially inoculated into raw pork macerated with enrichment broth. And then it was 10-fold diluted from $5.2{\times}10^{8}CFU/ml$ to 5.2 CFU/ml. The IC strip could detect $5.2{\times}10^{6}CFU/ml$ before enrichment. However, the lowest limit of detection was 5.2 CFU/ml after overnight incubation. The results indicated that the IC assay was a rapid, economical and simple method with high specificity and sensitivity for the detection of Salmonella spp. without using any equipment.

• Journal of IKEEE
• /
• v.24 no.4
• /
• pp.1086-1092
• /
• 2020

An autonomous agent for real world should be able to recognize text in scenes. With the advancement of deep learning, various DNN models have been utilized for transformation, feature extraction, and predictions. However, the existing state-of-the art STR (Scene Text Recognition) engines do not achieve the performance required for real world applications. In this paper, we introduce a performance-improvement method through an add-on composed of an OCR (Optical Character Recognition) engine and a classifier for STR engines. On instances from IC13 and IC15 datasets which a STR engine failed to recognize, our method recognizes 10.92% of unrecognized characters.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.5
• /
• pp.203-211
• /
• 1996

This paper describes CAD tools for the construction of image database in IC chip analysis CAD system. For IC chip analysis by high-resolution microscopy, the image database is essential to manage more than several thousand images. But manual database construction is error-prone and time-consuming. In order to solve this problem, we develop a set of CAD toos that include image grabber to capture chip images, image editor to make the whole chip image database from the grabbed images, and image divider to reconstruct the database that consists of evenly overlapped images for efficient region search. we also develop an interactive pattern matching method for user-friendly image editing, and a heuristic region search method for fast image division. The tools are developed with a high-performance graphic hardware with JPEG image comparession chip to process the huge color image data. The tools are under the field test and experimental resutls show that the database construction time can be redcued in 1/3 compared to manual database construction.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.64 no.4
• /
• pp.592-597
• /
• 2015

3D-IC is a novel semiconductor packaging technique stacking dies to improve the performance as well as the overall size. TSV is ideal for 3D-IC because it is convenient for stacking and excellent in electrical characteristics. However, due to high-density and micro-size of TSVs, they should be tested with a non-invasive manner. Thus, we introduce a TSV test method on test prober without a direct contact in this paper. A capacitive coupling effect between a probe tip and TSV is used to discriminate small TSV faults like voids and pin-holes. Through EM simulation, we can verify the size of eye-patterns with various frequencies is good for TSV test tools and non-contact test will be promising.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.26 no.8
• /
• pp.56-64
• /
• 2012

This paper proposes a novel maximum power point tracking (MPPT) control algorithm considering radiation to improve efficiency of PV system. The proposed algorithm is composed perturb and observe (PO) method and constant voltage (CV) method. PO method is simple to realize and CV method is possible to tracking MPP with low radiation. Response characteristics of proposed algorithm are compared to conventional MPPT algorithm such as PO method, IC method and CV method with radiation variation. This paper proves the validity of proposed algorithm through the analysis results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.20 no.4
• /
• pp.56-64
• /
• 2006

Generally, Permanent Magnet Brushless DC Motor(PM BLDC) is necessary the Hall-IC to detect the rotor position. But it will take place the operation standstill of motor or error of rotor position detection according to the circumference temperature, humidity, or limited surroundings. This paper propose the algorithm of rotor position detection only using one or two Hall-IC. Therefore we can estimate information of the others phase in sequence through a rotor instead of using three Hall-IC at 3 phase motor. This paper identify the same characteristics, performance and function of protection circuit by the proposed algorithm with the 3 phase PM BLDC motor in comparison with general method.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.6
• /
• pp.1068-1073
• /
• 1987

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.85-88
• /
• 2001

This paper suggests an improved switch architecture for the rechargeable battery protection IC. In the existing protection IC, charging and discharging switches composed of the CMOS transistor and the diode are external components. It is difficult to integrate the switches in a CMOS process due to the large chip-size overhead and inevitable parasitic effects. In this paper, we propose a new switch architecture of the MOSFET's 'diode connection' method. The performance and chip-size overhead are proved to be adequate for the fully integrated protection IC.

• Proceedings of the KIEE Conference
• /
• 1998.07f
• /
• pp.2085-2087
• /
• 1998

This paper presents the design method of a dimming electronic ballast for fluorescent lamps using a frequency control IC, and investigates the effects of circuit variables on its dimming characteristics. It is shown that effective dimming is possible with IC IR2151 for frequency control, and this leads to a feasible design of more smaller and cheaper dimming ballast. Five ballasts different in the values of the series inductance and capactance are designed, and their dimming characteristics are compared. As the result, the dimming range becomes more broader as the series inductance gets smaller and the capacitance larger. Thus appropriate selection of the values of L and C should be made according to the types of application site.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.26 no.4
• /
• pp.14-21
• /
• 2012

This paper study a method of modeling and simulation of LED driver circuit for a design optimization. Simplified LED modeling is introduced and a driver IC, HV9910, is modeled by implementing the major function blocks. Circuit of buck type converter is constructed for simulation. Simulation includes not only the internal function of IC but also the various performance results such as LED array current control and dimming. Experiment results are also shown to prove the verification of its usage. This results show that the simulation approach is valid for a circuit optimization and a reduction of development time.