• Journal of Power Electronics
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• 제7권4호
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• pp.310-317
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• 2007

In this paper, an analysis and hysteretic controller design of a $3^{rd}$ order buck converter is presented. The proposed hysteretic controller consists of an inner current-loop, just like the conventional cascade control scheme, and an outer voltage-loop for load voltage regulation. Although it is possible to include an inner current loop from different branches of the converter, from the feasibility and operational point of view, the load side capacitor current would be the better choice. The addition of an inner current-loop improves the dynamic performance of the converter while preserving the robustness of the hysteretic control. The controller formulation and closed-loop converter performance analysis are validated through computer simulations. Few experimental results of the proposed converter are given and compared with the buck converter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.471-476
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• 2015

This paper describes a CMOS hysteretic DC-DC buck converter with a constant switching frequency for mobile applications. The inherent problems of a large output ripple voltage that the conventional hysteretic DC-DC buck converters has faced have been resolved by using the proposed DC-DC buck converter which employed a ramp generator circuit to be able to increase a switching frequency. The proposed architecture enables the settling response time of charge pump circuit within the converter to become less than 6us suitable for mobile applications. The proposed DC-DC buck converter was implemented by using 0.35 um BCDMOS process and die size was $1.37mm{\times}1.37mm$. The measurement results showed that the proposed circuit received the input of 3.7 V and generated output of 1.2 V with the output ripple voltages less than 20 mV under load currents of 100~400 mA at the fixed switching frequency of 2 MHz. The maximum efficiency of the proposed hysteretic buck converter was measured to be around 93%.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.615-623
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• 2016

The paper describes a hysteretic buck converter including a differentiator and an adaptive hysteresis window controller. Differentiating the feedback signal achieves ultra-fast switching of the buck converter. The adaptive hysteresis window control allows a monotonous operation with predictable noise spectrum, and gives way to efficient design for variable supply and output voltages. The measurement results in a $0.13-{\mu}m$ CMOS process indicated that the switching frequency became double times higher, and the voltage ripple was reduced by up to 69%. They also indicated that the normalized switching frequency variation was reduced by 74% with variable $V_{DD}$ and by 63% with variable $V_{OUT}$. The power efficiency was improved by 3.5% depending on loading condition.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1038-1040
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• 1993

Single phase AC to DC Boost-converter which is control led with a variable hysteretic current mode for improvent of input power factor makes high power factor possible. Power Factor correction circuit can be identified with a determination of each parameters. A simaluation and experiment result to load and parameter variation is examined.

• 전자공학회논문지
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• 제52권6호
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• pp.50-56
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• 2015

본 논문에서는 모바일 응용에 적합한 고효율의 빠른 응답 특성을 가지는 히스테리틱 벅 변환기를 제안한다. 기존 히스테리틱 변환기의 문제점인 큰 출력 전압 리플과 작은 용량의 전력 인덕터 사용의 어려움을 삼각파 신호 발생기를 통해 해결하였다. 그리고 부하 전류에 따라 가변하는 스위칭 주파수를 PLL(Phase Locked Loop)구조를 사용하여 일정하게 함으로써 주변 IC에 미치는 EMI(Electro Magnetic Interference)잡음을 최소화 하였다. 이 회로는 BCDMOS 0.35um 2-poly 4-metal 공정으로 제작되었으며, 측정 결과 입력전압 3.7V, 출력전압 1.2V 부하 전류 50~500mA 범위에서 20mV 이하의 출력 전압 리플을 나타내며 170mA 이상의 부하 전류를 구동하는 경우 2MHz의 고정된 스위칭 주파수에서 동작하였다.

• 전기전자학회논문지
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• 제18권1호
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• pp.128-133
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• 2014

본 논문에서는 출력 리플 전압을 온도에 따라 개선시킬 수 있는 서미스터를 이용한 히스테리틱 벅 변환기를 제안한다. 회로가 민감 할 수 있는 높은 온도에서는 두 비교 전압을 비교적 크게 결정하지만, 회로가 안정적으로 동작 할 수 있는 온도에서는 두 비교 전압을 작게 결정하여, 출력 리플 전압을 최소화 시킨다. 모의실험결과는 출력 리플 전압을 30mV이상 감소시켰으며, 로드 레귤레이션은 0.011mV/mA 이다. 제안하는 회로는 빠른 응답과 저 전력이 요구되는 디지털 회로를 구동하는 전원 관리 회로로서 활용되기 적합하다.

• Journal of Power Electronics
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• 제15권2호
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• pp.378-388
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• 2015

This paper proposes a pulse width modulation (PWM)-based sliding mode controller (SMC) for a full-bridge DC-DC converter that can eliminate static output voltage error. Hysteretic SMC in DC-DC converter does not have a fixed switching frequency, and applying hysteretic SMC to full-bridge converters is difficult. Fixed-frequency SMC, which is also called PWM-based SMC, based on equivalent control overcomes these shortcomings. However, the controller order reduction in equivalent control in PWM-based SMC causes static output voltage error. To resolve this issue, an integral item is added to the PWM-based SMC. Sliding mode coefficients are designed by applying a standard second-order system to the sliding mode surface. The effect of adding an integral item on the controller is analyzed, and an integral coefficient design method is proposed. Experiment results on a three-level full-bridge DC-DC converter verify the control scheme and design method proposed in this paper.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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• pp.85-87
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• 2009

Due to the enormous progress in light emitting diodes (LEDs), LEDs have been become a good solution for lightings. In LED driver for lighting applications, it is required a high input voltage to drive more LEDs. Therefore, a high-voltage should be changed to low-voltage to supply power for drive IC. In this paper, a LED drive IC with hysteretic-buck converter topology using a voltage clamp bias circuit was proposed and verified through simulations.

• 한국통신학회논문지
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• 제42권4호
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• pp.864-870
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• 2017

본 논문은 넓은 부하 전류를 요구하는 휴대 기기에서 사용될 목적으로 주파수 전압 변환을 이용하여 모드 제어 가능한 듀얼 모드 벅 변환기를 설명한다. 기존의 히스테스테릭 벅 변환기의 문제인 저 부하에서의 PLL 보상 및 효율 저하를 제안하는 듀얼 벅 변환기의 개선된 PFM 모드를 통해 해결한다. 또한 기존의 듀얼 모드 벅 변환기의 주요 회로인 모드 제어기에서의 부하 변화 감지의 어려움과 느린 모드 전환 속도를 제안하는 모드 제어기로 개선 시킨다. 제안하는 모드 제어기는 최소 1.5us의 모드 전환 시간을 가진다. 제안하는 DC-DC 벅 변환기는 $0.18{\mu}m$ CMOS 공정에서 설계하였으며 칩 면적은 $1.38mm{\times}1.37mm$이다. 기생 소자를 포함한 인덕터와 커패시터를 고려한 후 모의실험 결과는 1~500mA의 부하 전류 범위에서 입력 전압을 2.7~3.3V를 가지며 PFM 모드는 65mV이내, 히스테리틱 모드에서는 고정된 스위칭 주파수 상태에서 16mV의 출력 리플 전압을 가지는 1.2V의 출력 전압을 생성한다. 제안하는 듀얼 모드 벅 변환기의 최대 효율은 80mA에서 95%를 나타내며 해당 전체 부하 범위에서 85% 이상의 효율을 지닌다.

• Journal of Power Electronics
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• 제10권2호
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• pp.115-124
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• 2010

In this paper, a simple yet efficient auto mode-hop ripple control structure for buck converters with light load operation enhancement is proposed. The converter, which operates under a wide range of input and output voltages, makes use of a state-dependent hysteretic comparator. Depending on the output current, the converter automatically changes the operating mode. This improves the efficiency and reduces the output voltage ripple for a wide range of output currents for given input and output voltages. The sensitivity of the output voltage to the circuit elements is less than 14%, which is seven times lower than that for conventional converters. To assess the efficiency of the proposed converter, it is designed and implemented with commercially available components. The converter provides an output voltage in the range of 0.9V to 31V for load currents of up to 3A when the input voltage is in the range of 5V to 32V. Analytical design expressions which model the operation of the converter are also presented. This circuit can be implemented easily in a single chip with an external inductor and capacitor for both fixed and variable output voltage applications.