• Journal of Internet Computing and Services
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• v.16 no.5
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• pp.19-27
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• 2015

Due to the advantages of fast read/write operation and low power consumption, SSD(Solid State Drive) is now widely adopted as storage device of smart phone, laptop computer, server, etc. However, the shortcomings of SSD such as limited number of write operations and asymmetric read/write operation lead to the problem of shortened life span of SSD. Therefore, the block replacement policy of SSD used as cache for HDD is very important. The existing solutions for improving the lifespan of SSD including the LARC scheme typically employ the LRU algorithm to manage the SSD blocks, which may increase the miss rate in SSD due to the replacement of frequently used block instead of rarely used block. In this paper we propose a novel block replacement scheme which considers the block reuse interval to effectively handle various data read/write patterns. The proposed scheme replaces the block in SSD based on the recency decided by reuse interval and age along with hit ratio. Computer simulation using workload trace files reveals that the proposed scheme consistently improves the performance and lifespan of SSD by increasing the hit ratio and decreasing the number of write operations compared to the existing schemes including LARC.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.789-793
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• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• The KIPS Transactions:PartC
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• v.12C no.2 s.98
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• pp.243-250
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• 2005

To introduce the cache in a client is one of the methods to migrate the performance degradation of broadcast systems doe to the inherent restrictions of wireless communication environments such as low bandwidth or frequent disconnections. In this paper, we propose a pull-based broadcast strategy in hybrid-based data broadcast systems using bit vectors in order to effectively broadcast data recently requested by clients. Then, we propose a caching strategy considering the characteristics of data broadcast algorithm and then evaluate the performance of the system. According to the result of evaluation, the system employing the proposed strategies shows the better performance in terms of response time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.3
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• pp.1481-1501
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• 2019

In opportunistic network, the behavior of a node is autonomous and has social attributes such as selfishness.If a node wants to forward information to another node, it is bound to be limited by the node's own resources such as cache, power, and energy.Therefore, in the process of communication, some nodes do not help to forward information of other nodes because of their selfish behavior. This will lead to the inability to complete cooperation, greatly reduce the success rate of message transmission, increase network delay, and affect the overall network performance. This article proposes a hybrid incentive mechanism (Mim) based on the Reputation mechanism and the Credit mechanism.The selfishness model, energy model (The energy in the article exists in the form of electricity) and transaction model constitute our Mim mechanism. The Mim classifies the selfishness of nodes and constantly pay attention to changes in node energy, and manage the wealth of both sides of the node by introducing the Central Money Management Center. By calculating the selfishness of the node, the currency trading model is used to differentiate pricing of the node's services. Simulation results show that by using the Mim, the information delivery rate in the network and the fairness of node transactions are improved. At the same time, it also greatly increases the average life of the network.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• Journal of KIISE:Databases
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• v.37 no.6
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• pp.308-314
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• 2010

As the price of flash memory continues to drop and the technology of flash SSD controller innovates, high performance flash SSDs with affordable prices flourish in the storage market. Nevertheless, it is hard to expect that flash SSDs will replace harddisks completely as database storage. Instead, the approach to use flash SSD as a cache for harddisks would be more practical, and, in fact, several hybrid storage architectures for flash memory and harddisk have been suggested in the literature. In this paper, we propose a new approach to use flash SSD as an extended buffer for main buffer in database systems, which stores the pages replaced out from main buffer and returns the pages which are re-referenced in the upper buffer layer, improving the system performance drastically. In contrast to the existing approaches to use flash SSD as a cache in the lower storage layer, our approach, which uses flash SSD as an extended buffer in the upper host, can provide fast random read speed for the warm pages which are being replaced out from the limited main buffer. In fact, for all the pages which are missing from the main buffer in a real TPC-C trace, the hit ratio in the extended buffer could be more than 60%, and this supports our conjecture that our simple extended buffer approach could be very effective as a cache. In terms of performance/price, our extended buffer architecture outperforms two other alternative approaches with the same cost, 1) large main buffer and 2) more harddisks.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.38 no.1
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• pp.71-79
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• 2014

A parallelization of the bi-conjugate gradient solver for the pressure equation of the CUPID (component unstructured program for interfacial dynamics) code, which was developed for analyzing the components of a pressurized water-cooled reactor, was studied in a symmetric multi-processing system. The parallel performance was investigated for three typical parallel programming models (MPI, OpenMP, Hybrid) by solving incompressible backward-facing step flow at various grid resolutions. It was confirmed that parallel performance was low when problem size was small or the memory requirement for each thread was considerably higher than the cache memory. Furthermore, it was shown that MPI was better than OpenMP regardless of the problem size, and Hybrid was the best when the number of threads was relatively small.

• Journal of Korea Multimedia Society
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• v.9 no.2
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• pp.244-254
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• 2006

This paper presents an efficient hybrid technique to compact the trie indexing the huge forward table small enough to be stored into cache for speeding up IP lookup. It combines two techniques, an encoding scheme called bit-map and a controlled-prefix expanding scheme to replace slow memory search with few fast-memory accesses and computations. For compaction, the bit-map represents each index and child pointer with one bit respectively. For example, when one node denotes n bits, the bit-map gives a high compression rate by consumes $2^{n-1}$ bits for $2^n$ index and child link pointers branched out of the node. The controlled-prefix expanding scheme determines the number of address bits represented by all root node of each trie's level. At this time, controlled-prefix scheme use a dynamic programming technique to get a smallest trie memory size with given number of trie's level. This paper proposes standard that can choose suitable trie structure depending on memory size of system and the required IP lookup speed presenting optimal memory size and the lookup speed according to trie level number.

• Structural Engineering and Mechanics
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• v.25 no.2
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• pp.239-268
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• 2007

This paper deals with optimal stacking sequence design of laminate composite structures. The stacking sequence optimisation of laminate composites is formulated as a combinatorial problem and is solved using Simulated Annealing (SA), an algorithm devised based on inspiration of physical process of annealing of solids. The combinatorial constraints are handled using a correction strategy. The SA algorithm is strengthened by embedding Tabu search in order to prevent recycling of recently visited solutions and the resulting algorithm is referred to as tabu embedded simulated Annealing (TSA) algorithm. Computational performance of the proposed TSA algorithm is enhanced through cache-fetch implementation. Numerical experiments have been conducted by considering rectangular composite panels and composite cylindrical shell with different ply numbers and orientations. Numerical studies indicate that the TSA algorithm is quite effective in providing practical designs for lay-up sequence optimisation of laminate composites. The effect of various neighbourhood search algorithms on the convergence characteristics of TSA algorithm is investigated. The sensitiveness of the proposed optimisation algorithm for various parameter settings in simulated annealing is explored through parametric studies. Later, the TSA algorithm is employed for multi-criteria optimisation of hybrid composite cylinders for simultaneously optimising cost as well as weight with constraint on buckling load. The two objectives are initially considered individually and later collectively to solve as a multi-criteria optimisation problem. Finally, the computational efficiency of the TSA based stacking sequence optimisation algorithm has been compared with the genetic algorithm and found to be superior in performance.

• Convergence Security Journal
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• v.6 no.4
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• pp.91-99
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• 2006

Generally, a study of web caching is conducted on a performance improvement with structural approaches and a new hybrid method using existing methods, and studies on caching method itself. And existing analysis of reference-characteristic are conducted on a history analysis and a preference of users, a view point of data mining by log analysis. In this study, we analyze the reference-characteristic of web object on a view point of a characteristic of probability-distribution and a mean value of lifetime of a web-object. And using this result, we propose the new method for a performance improvement of a web-caching.