• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2006.03a
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• pp.563-570
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• 2006

Distributed control architecture is based on sharing control and data between multiple nodes on a network Communication and task sharing can be distributed between multiple control computers. Although many communication protocols exist, such as TCP/IP and UDP, they do not have the determinism that realtime control demands. Fiber-optic reflective shared memory creates the opportunity for realtime distributed control. This architecture allows control and computational tasks to be divided between multiple systems and operate in a deterministic realtime environment. One such shared memory architecture is based on Curtiss-Wright ScramNET family of fiber-optic reflective memory. MTS has built seismic and structural control software and hardware capable of utilizing ScramNET shared memory, opening up infinite possibilities in research and new capabilities in Hybrid and Model-In-The-Loop control.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.240-242
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• 2009

Flash memories are one of best media to support future computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation of SSD. Due to the unique characteristics of flash media and hard disk, the efficiency of I/O processing is severely reduced without special treatment, especially in the presence of heavy workload or bulk data copy. In this respect, we need to design and develop efficient hybrid-RAID storage system.

• Journal of Electrical Engineering and Technology
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• v.11 no.5
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• pp.1457-1465
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• 2016

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.93-96
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• 2013

모바일 환경에서 전력 손실이 중요한 문제 중 하나가 됨에 따라, MRAM과 플래시메모리와 같은 비 휘발성 메모리가 차세대 모바일 컴퓨터에 널리 사용될 것이다. 본 논문에서는 DRAM/MRAM 하이브리드 메인 메모리의 제한적인 쓰기 연산 성능을 고려한 효율적인 버퍼 캐시 기법을 연구했다. 제안한 기법은 MRAM 의 제한적인 쓰기 연산 성능을 고려하고 플래시 메모리 저장 장치의 삭제 연산 횟수를 최소화한다.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.1-13
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• 2009

Flash memory is widely used as a storage medium of mobile devices such as MP3 players, cellular phones and digital cameras due to its tiny size, low power consumption and shock resistant characteristics. Currently, there are many studies to replace HDD with flash memory because of its numerous strong points. To use flash memory as a storage medium, FTL(Flash Translation Layer) is required since flash memory has erase-before-write constraints and sizes of read/write unit and erase unit are different from each other. Recently, new type of flash memory called "large block flash memory" is introduced. The large block flash memory has different physical structure and characteristics from previous flash memory. So existing FTLs are not efficiently operated on large block flash memory. In this paper, we propose an efficient FTL for large block flash memory based on FAST(Fully Associative Sector Translation) scheme and page-level mapping on data blocks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Journal of information and communication convergence engineering
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• v.21 no.2
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• pp.159-166
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• 2023

The COI gene is a sequence of approximately 650 bp at the 5' terminal of the mitochondrial Cytochrome c Oxidase subunit I (COI) gene. As an effective DeoxyriboNucleic Acid (DNA) barcode, it is widely used for the taxonomic identification and evolutionary analysis of species. We created a CNN-LSTM hybrid model by combining the gene features partially extracted by the Long Short-Term Memory ( LSTM ) network with the feature maps obtained by the CNN. Compared to K-Means Clustering, Support Vector Machines (SVM), and a single CNN classification model, after training 278 samples in a training set that included 15 genera from two orders, the CNN-LSTM hybrid model achieved 94% accuracy in the test set, which contained 118 samples. We augmented the training set samples and four genera into four orders, and the classification accuracy of the test set reached 100%. This study also proposes calculating the cosine similarity between the training and test sets to initially assess the reliability of the predicted results and discover new species.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• Journal of Information Display
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• v.10 no.4
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• pp.149-157
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• 2009

Reported herein is the architecture for a nonvolatile n-type memory paper field-effect transistor. The device was built via the hybrid integration of natural cellulose fibers (pine and eucalyptus fibers embedded in resin with ionic additives), which act simultaneously as substrate and gate dielectric, using passive and active semiconductors, respectively, as well as amorphous indium zinc and gallium indium zinc oxides for the gate electrode and channel layer, respectively. This was complemented by the use of continuous patterned metal layers as source/drain electrodes.