• Journal of the Korean Institute of Intelligent Systems
• /
• v.18 no.5
• /
• pp.611-616
• /
• 2008

Error correcting codes (ECCs) are commonly used to protect against the soft errors. Single error correcting and double error detecting (SEC-DED) codes are generally used for this purpose. The proposed approach in this paper selectively reduced power consumption, delay, and area in single-error correcting, double error-detecting checker circuits that perform memory error correction. The multi-objective genetic algorithm is employed to solve the non -linear optimization problem. The proposed method allows that user can choose one of different non-dominated solutions depending on which consideration is important among them. Because we use multi-objective genetic algorithm, we can find various dominated solutions. Therefore, we can choose the ECC according to the important factor of the power, delay and area. The method is applied to odd-column weight Hsiao code which is well- known ECC code and experiments were performed to show the performance of the proposed method.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.19 no.2
• /
• pp.180-184
• /
• 2009

The memory is very sensitive to the soft error because the integration of the memory increases under low power environment. Error correcting codes (ECCs) are commonly used to protect against the soft errors. This paper proposes a new genetic ECC design method which reduces power consumption. Power is minimized using the degrees of freedom in selecting the parity check matrix of the ECCs. Therefore, the genetic algorithm which has the novel genetic operators tailored for this formulation is employed to solve the non-linear power optimization problem. Experiments are performed with Hamming code and Hsiao code to illustrate the performance of the proposed method.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.1135-1136
• /
• 2008

Error correcting codes (ECC) are widely used in all types of memory in industry, including caches and embedded memory. The focus in this paper is on studying of power consumption in memory ECCs circuitry that provides single error correcting and double error detecting (SEC-DED) designed by various evolution strategies. The methods are applied to two commonly used SEC-DED codes: Hamming and odd column weight Hsiao codes. Finally, we conduct some simulations to show the performance of the various methods.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.8
• /
• pp.111-121
• /
• 1994

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.1
• /
• pp.43-49
• /
• 2008

In this paper, a method using the Ant Colony Optimization(ACO) is proposed for reducing the power consumption of memory ECC checker circuitry which provide Single-Error Correcting and Double-Error Detecting(SEC-DED). The H-matrix which is used to generate SEC-DED codes is optimized to provide the minimum switching activity with little to no impact on area or delay using the symmetric property and degrees of freedom in constructing H-matrix of Hsiao codes. Experiments demonstrate that the proposed method can provide further reduction of power consumption compared with the previous works.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.7 s.349
• /
• pp.132-142
• /
• 2006

In this paper, we present a candidate high data rate space time coded OFDM system for short range personal networking. The system transmits the complex space time coded signals with a hybrid orthogonal frequency division multiplexing (OFDM) based on ultra wideband (UWB) pulses. The transmitted signals are sparse pulse trains modulated by a frequency selected from a properly designed set of frequencies. Additionally, a widely linear (WL) receive filter and a space time frequency transmission are designed by using two simple parallel linear detectors. To overcome the deeply fade in the propagation system, a beamforming combined with space time block codes also 따 e briefly discussed.