• Journal of Power Electronics
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• 제16권3호
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• pp.960-969
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• 2016

High-power three-level voltage-source converters are widely utilized in high-performance AC drive systems. In several ultra-power instances, the harmonics on the grid side should be reduced through multiple rectifications. A combined harmonic elimination method that includes a dual primary-side series-connected winding transformer and selective harmonic elimination pulse-width modulation is proposed to eliminate low-order current harmonics on the primary and secondary sides of transformers. Through an analysis of the harmonic influence caused by dead time and DC magnetic bias, a synthetic compensation control strategy is presented to minimize the grid-side harmonics in the dual primary side series-connected winding transformer application. Both simulation and experimental results demonstrate that the proposed control strategy can significantly reduce the converter input current harmonics and eliminates the DC magnetic bias in the transformer.

• 한국컴퓨터정보학회논문지
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• 제7권3호
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• pp.109-114
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• 2002

본 연구에서는 기존의 Colpitts VCO에서 바이어스 저항에 의한 성능 저하문제를 간단한 트랜지스터의 모델을 사용하여 분석하고, 발진기의 성능을 저하시키는 바이어스 저항의 영향을 제거하는 새로운 구조를 제시한다. 또한 이를 이용하여 차세대 이동통신용 소형, 저 전력 VCO를 설계하고 제작하였다.

• 대한기계학회논문집A
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• 제32권10호
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• pp.831-835
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• 2008

We present a continuous electrical cell lysis chip, using a DC bias voltage to generate the focused high electric field for cell lysis as well as the electroosmotic flow for cell transport. The previous cell lysis chips apply an AC voltage between micro-gap electrodes for cell lysis and use pumps or valves for cell transport. The present DC chip generates high electrical field by reducing the width of the channel between a DC electrode pair, while the previous AC chips reducing the gap between an AC electrode pair. The present chip performs continuous cell pumping without using additional flow source, while the previous chips need additional pumps or valves for the discontinuous cell loading and unloading in the lysis chambers. The experimental study features an orifice whose width and length is 20 times narrower and 175 times shorter than the width and length of a microchannel. With an operational voltage of 50 V, the present chip generates high electric field strength of 1.2 kV/cm at the orifice to disrupt cells with 100% lysis rate of Red Blood Cells and low electric field strength of 60 V/cm at the microchannel to generate an electroosmotic flow of $30{\mu}m/s{\pm}9{\mu}m/s$. In conclusion, the present chip is capable of continuous self-pumping cell lysis at a low voltage; thus, it is suitable for a sample pretreatment component of a micro total analysis system or lab-on-a-chip.

• ETRI Journal
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• 제34권6호
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• pp.885-891
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• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.204.1-204.1
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• 2015

We studied the electrical properties and gate bias stress (GBS) stability of thin film transistors (TFTs) with multi-stacked InZnO layers. The InZnO TFTs were fabricated via solution process and the In:Zn molar ratio was 1:1. As the number of InZnO layers was increased, the mobility and the subthreshold swing (S.S) were improved, and the threshold voltage of TFT was reduced. The TFT with three-layered InZnO showed high mobility of $21.2cm^2/Vs$ and S.S of 0.54 V/decade compared the single-layered InZnO TFT with $4.6cm^2/Vs$ and 0.71 V/decade. The three-layered InZnO TFTs were relatively unstable under negative bias stress (NBS), but showed good stability under positive bias stress (PBS).

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 추계학술대회
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• pp.533-536
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• 2016

본 논문에서는 진동 에너지를 이용한 MPPT 제어기능을 갖는 에너지 하베스팅 회로를 설계하였다. Body-bias technique과 bulk-driven technique을 이용하여 저전압에서도 높은 효율특성을 갖는 고성능 AC-DC 변환기를 제안하고 진동에너지 하베스팅 회로 설계에 적용하였다. MPPT (Maximum Power Point Tracking) 제어는 진동소자의 개방회로전압과 MPP 전압간의 관계를 이용하였으며, 진동소자의 개방회로전압을 주기적으로 샘플링 함으로써 이를 이용해 MPPT 기준전압을 생성하고, 이를 기준으로 부하로의 에너지 공급을 제어한다. $0.35{\mu}m$ CMOS 공정으로 설계된 회로의 칩 면적은 $1.21mm{\times}0.98mm$이다.

• 한국세라믹학회지
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• 제32권3호
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• pp.371-377
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• 1995

Silicon oxide films were grown on single-crystal silicon substrates at low temperatures (25~205$^{\circ}C$) in a low pressure electron cyclotron resonance (ECR) oxygen plasma. The growth rate of the silicon oxide film increased as the temperature increased or the pressure decreased. Also, the thickness of the silicon oxide film increased at negative bias voltage, but not changed at positive bias voltage. The growth law of the silicon oxide film was approximated to the parabolic form. Capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were studied using Al/SiO2/p-Si MOS structures. For a 10.2 nm thick silicon oxide film, the leakage current density at the electric field of 1 MVcm-1 was less than 1.0$\times$10-8Acm-2 and the breakdown field was higher than 10 MVcm-1. The flat band voltage of Al/SiO2/p-Si MOS capacitor was varied in the range of -2~-3 V and the effective dielectric constant was 3.85. These results indicate that high quality oxide films with properties that are similar to those of thermal oxide film can be fastly grown at low temperature using the ECR oxygen plasma.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.79-99
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• 2010

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

• 한국표면공학회지
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• 제50권6호
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• pp.473-479
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• 2017

CrN coatings have been used as protective coatings for cutting tools, forming tools, and various tribological machining applications because these coatings have high hardness. Cr-Al-N coatings have been investigated to improve the properties of CrN coatings. Cr-Al-N coatings were fabricated by a hybrid physical vapor deposition method consisting of unbalanced magnetron sputtering and arc ion plating with different working pressure and substrate bias voltage. The phase analysis of the composition was performed using XRD (x-ray diffraction). Cr-Al-N coatings were grown with textured CrN phase and (111), (200), and (220) planes. The adhesion strength of the coatings tested by scratch test increased. The friction coefficient and removal rate of the coatings were measured by a ball-on-disk test. The friction coefficient and removal rate of the coatings decreased from 0.46. to 0.22, and from $2.00{\times}10^{-12}m^2/N$ to $1.31{\times}10^{-13}m^2/N$, respectively, with increasing bias voltage. The tribological properties of the coatings increased with increasing substrate bias voltage.

• Tribology and Lubricants
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• 제35권1호
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• pp.1-8
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• 2019

Demand for plastic gears are increasing in many industries due to their low production cost, light weight, applicability without lubricant, corrosion resistance and high resilience. Despite these benefits, utilizing plastic gears is limited due to their poor material properties. In this work, DLC coating was applied to improve the tribological properties of polyamide66 gear. 0 V, 40 V, and 70 V of negative bias voltages were selected as a deposition parameter in DC magnetron sputtering system. Pin-on-disk experiment was performed in order to investigate the wear characteristics of the gears. The results of the pin-on-disk experiment showed that DLC coated polyamide66 with 40 V of negative bias voltage had the lowest friction coefficient value (0.134) and DLC coated PA66 with 0 V of negative bias voltage showed the best wear resistance ($9.83{\times}10^{-10}mm^3/N{\cdot}mm$) among all the specimens. Based on these results, durability tests were conducted for DLC coated polyamide66 gears with 0 V of negative bias voltage. The tests showed that the temperature of the uncoated polyamide66 gear increased to about $37^{\circ}C$ while the DLC coated gear saturated at about $25^{\circ}C$. Also, the power transmission efficiency of the DLC coated gear increased by about 6% compared to those without coating. Weight loss of the polyamide66 gears were reduced by about 73%.