• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 A
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• pp.709-711
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• 2005

Developing fault location system for underground power cable which can detect its fault location exactly require very high speed data acquisition and signal processing capability. We are developing fault location system which is different from conventional fault locator. This fault location system monitor underground power cable by using on-line speed current sensor and if there are an accident, it record its transient signal and calculate fault location by analyzing it. Signals which acquired when power cable fault arise, showed transient characteristics and its frequency band is very hish. So, to develop fault location system, we designed special high speed data acquisition and signal processing board. In this thesis, we describe on data acquisition and signal processing H/W design for fault location system on underground power cable.

• Current Optics and Photonics
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• 제2권1호
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• pp.53-58
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• 2018

A novel X-band high speed frequency sweep signal generator based on a tunable optoelectronic oscillator (OEO) incorporating a frequency-swept laser is presented and the theoretical fundamentals of the design are explained. A prototype of the generator with tuning range from 8.8552 GHz to 10.3992 GHz and a fine step about 8 MHz is achieved. The generated radiofrequency signal with a single sideband (SSB) phase noise lower than -100 dBc/Hz@10KHz is experimentally demonstrated within the whole tunable range, without any narrow RF band-pass filters in the loop. And the tuning speed of the frequency sweep signal generator can reach to over 1 GHz/s benefiting from applying a novel dispersion compensation modular instead of several tens of kilometers of optical fiber delay line in the system.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2005년도 춘계학술대회 논문집
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• pp.757-766
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• 2005

A speed of a train is controlled by Automatic Train Control system and the continuous transmission system provide the speed related information in the Korean High Speed Line. The primary objective of this paper is to measure the level of continuous signal and to calculate the message of that signal. A measuring equipment is introduced and the equipment provide the base line of the level of current and the correction information of the message.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권8호
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• pp.451-458
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• 2000

The precise speed and position control technique for Brushless DC Motor demands accurate position and speed feedback information. Generally, resolver or absolute encoders are used as speed and positiion sensor. But they increase cost and more problem happens at low speed than high speed specially. Therefore, in this paper, optimal speed observer is proposed for decreasing size and cost of whole system. And also, we consider the error problem about the system modeling and measurement at low speed range as well as high speed. The overall system consists of two parts, a drive and a speed observer. We make use of Least square curve fitting algorithm as speed observer and can overcome low resolution by proposed observer. Also, because of using the signal of hall sensor, robust control is possible in low speed as well as high speed for the change of the parameters of the system and disturbance. To construct observer using the signal of hall sensor, we design the pulse multiplier circuit and the software of microprocessor, AT89CC2051. Finally, the performance of the proposed observer is exemplified by some simulations and experiments.

• ETRI Journal
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• 제25권5호
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• pp.418-421
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• 2003

We propose an unbiased signal-to-interference ratio (SIR) estimator for the high speed downlink packet access (HSDPA) system. The proposed SIR estimator solves the problem of underestimation present in conventional SIR estimators and is suitable for channel quality measurement in the adaptive modulation and coding scheme of HSDPA, which requires accurate SIR estimation for optimum adaptive modulation and coding selection. Our analysis and simulation results demonstrate the improved estimation performance of the proposed SIR estimator.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.182-185
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• 1998

This paper describes a field orientation control of an induction motor without any speed transducer and proposes a wide-range speed control strategy with the field orientation algorithm. The difference at impedances between the direct and quadrature axis at the injected signal is used for the sensorless field orientation control. But this algorithm has some limitations and should be supported by other method at high speed. In this paper, a sensorless speed control at an induction motor for wide speed range operation is proposed. The proposed algorithm is verified by experimental results.

• Progress in Superconductivity
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• 제4권1호
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• pp.74-79
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• 2002

High-speed probe made to test single flux quantum(SFQ) circuits was comprised of semi-rigid coaxial cables and microstrip lines. The impedance was set at 50 $\Omega$to carry high-speed signals without much loss. To do performance test of high-speed probe, we have attempted to fabricate a test chip which has a coplanar waveguide(CPW) structure. Electromagnetic simulation was done to optimize the dimension of CPW so that the CPW structure has an impedance of 50$\Omega$, matching in impedance with the probe. We also used the simulation to investigate the effect of the width of signal line and the gap between signal line and ground plane to the characteristics of CPW structure. We fabricated the CPW structure with a gold film deposited on Si wafer whose resistivity was above $1.5\times$10$_4$$\Omega$.cm. The magnitudes of S／sub 21／ of CPW at 6 ㎓ in simulations and in the actual measurements done with a network analyzer were: -0.1 ㏈ and -0.33 ㏈ (type A),-0.2 ㏈ and -0.48 ㏈ (type B), respectively. Using the test chip, we have successfully tested the performance of high-speed probe made for SFQ circuits. The probe showed the good performance overthe bandwidth of 10 ㎓.

• ETRI Journal
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• 제29권6호
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• pp.835-837
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• 2007

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.