• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• ETRI Journal
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• v.41 no.5
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1741-1744
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• 2003

This study is a kind of preliminary research in order to propose and suggest the plan of performance improvement for the speed-up through the examination of operational condition on the field for signal system facility on the conventional railway, in order to obtain the elemental technology from the technical development for utilization of high speed train which will be run on the Korea Conventional Line and, finally, in order to propose the specification of signal system using for high speed and the scheme of establishment for the optimal signal system.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.48-51
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• 2024

Recently, high-performance BLDC(Brushless DC) motors are being applied to various fields such as industrial and personal mobility devices and drones. To achieve the best performance of BLDC, sensors such as hall sensors, encoders, and resolvers are used to determine the position of the rotor, and various speed control technologies are being developed. However, due to problems with high-speed control due to external environmental factors and frequency bandwidth of semiconductor sensing devices, research on BLDC motors without semiconductor sensing devices is in progress. Therefore, in this study, a signal brush was added to the end of the rotor of a BLDC motor and the rotor position of the BLDC motor was detected by analyzing the signal output through the signal brush.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.386-389
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• 2013

In this paper, for signal integrity analysing high-speed signal between a processor and a DDR2 memory, transient analysis is done and eye diagrams are generated using IBIS models of IC chips and S-parameters of transmission line. From the eye diagrams of such high-speed signals as DQ, DQS/DQSb, Clock, Address and Control, signal quality is assured through measuring timing and voltage margins during setup and hold times and verifying that the over-/under-shoot and the cross points of differential signals satisfy their specifications.

• Journal of Power Electronics
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• v.9 no.4
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• pp.582-592
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• 2009

This paper proposes a new speed sensorless direct torque and flux controlled interior permanent magnet synchronous motor (IPMSM) drive. Closed-loop control of both the torque and stator flux linkage are achieved by using two proportional-integral (PI) controllers. The reference voltage vectors are generated by a SVM unit. The drive uses an adaptive sliding mode observer for joint stator flux and rotor speed estimation. Global asymptotic stability of the observer is achieved via Lyapunov analysis. At low speeds, the observer is combined with the high frequency signal injection technique for stable operation down to standstill. Hence, the sensorless drive is capable of exhibiting high dynamic and steady-state performances over a wide speed range. The operating range of the direct torque and flux controlled (DTFC) drive is extended into the high speed region by incorporating field weakening. Experimental results confirm the effectiveness of the proposed method.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.2 no.3
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• pp.13-19
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• 2003

The high speed machining technology has been improved remarkably in die/mold industry with the growth of parts and materials industries. Though the spindle speed of machine tool increases, the condition monitoring techniques of the machine tool, tool and workpiece in high speed machining ate incomplete. In tins study, efficient sensing technology in high speed machining is suggested by observing the characteristics of cutting force, gap sensor and accelerometer signal also, machinability of high-speed machining is experimentally evaluated sensing technique to monitor the machine tool and machining conditions was performed.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1582-1591
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• 2014

This paper presents a hybrid sensorless control for an interior permanent magnet synchronous motor (IPMSM) for zero-, low-, and high-speed regions. Many sensorless control methods such as an observer-based estimator have been introduced. However, most of the observer-based estimators have a disadvantage at start-up and in the low-speed region. To solve this problem, a simple strategy of using a hybrid system is proposed by integrating a high-frequency (HF) signal injection method and a full-order flux observer. In addition, an HF signal injection method with only a low pass filter (LPF) is proposed to simplify the hybrid system. The hybrid system achieves high-performance drive throughout the entire speed range. The effectiveness of the proposed hybrid technique is verified by experiments using an 11-kW IPMSM drive system.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.175-183
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• 2016

This paper brings out a novel method for reducing Near end and Far end Crosstalk using Electromagnetic Band Gap structures (EBG) in High Speed RF transmission lines. This work becomes useful in high speed closely spaced Printed Circuit Board (PCB) traces connected to multi core processors. By using this method, reduction of −40dB in Near-End Crosstalk (NEXT) and −60 dB in Far End Crosstalk (FEXT) is achieved. The results are validated through experimental measurements. Time domain analysis is performed to validate the signal integrity property of coupled transmission lines.