• Title/Summary/Keyword: High-speed signal

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The study of onboard signal control system for tilting (틸딩열차의 차상신호제어방식에 대한 연구)

  • Kim, You-Ho;Lee, Hoon-Koo;Lee, Soo-Hwan;Bae, June-Ki;Baek, Jong-Hyen
    • Proceedings of the KIEE Conference
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    • 2006.04b
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    • pp.301-303
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    • 2006
  • According to speed elevation of internal railroad, Seoul-Busan high-speed railway was opened up. Setting hereupon speed elevation of old line propel. Therefore, research and development about Tilting train are propel by one of method that do not need huge investment such as earthwork serving speed elevation of general railroad. Studied about car report lake this treatise applies in Tilting train's signal control.

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Detection of Rotating Speed of Induction Motor Using the Rotor Slot Harmonic (회전자 슬롯 고조파를 이용한 유도전동기의 회전속도 검출)

  • Yang, Chul-Oh;Lee, Gyeong-Seok;Lee, Dae-Sung;Parkk, Kyu-Nam;Song, Myung-Hyun
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.2077-2078
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    • 2011
  • Now a days, the induction motor is widely used in industry automation. Without monitoring the motor fault, maintenance cost is increased undesirably high. The slip frequency is included in the feature frequency, so rotating rotor speed is needed. In this paper, a sensorless motor speed estimation method, rotor slot harmonic(RSH) method is suggested and a solution of rotor bar diagnosis is proposed for motor running with light-load. When the rotor is rotating, it shows the harmonic signal of back-emf voltage related with number of rotor slot. So from the power spectrum of current signal, we can find the rotor speed.

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Fully Programmable Memory BIST for Commodity DRAMs

  • Kim, Ilwoong;Jeong, Woosik;Kang, Dongho;Kang, Sungho
    • ETRI Journal
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    • v.37 no.4
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    • pp.787-792
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    • 2015
  • To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

Low-clock-speed time-interleaved architecture for a polar delta-sigma modulator transmitter

  • Nasser Erfani Majd;Rezvan Fani
    • ETRI Journal
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    • v.45 no.1
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    • pp.150-162
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    • 2023
  • The polar delta-sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software-defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low-complexity timeinterleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four-branch timeinterleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal-tonoise-and-distortion ratio.

Improvement of Signal Processing Circuit for Inspecting Cracks on the Express Train Wheel (고속 신호처리 회로에 의한 고속철도 차륜검사)

  • Hwang, Ji-Seong;Lee, Jin-Yi;Kwon, Suk-Jin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.579-584
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    • 2008
  • A novel nondestructive testing (NDT) system, which is able to detect a crack with high speed and high spatial resolution, is urgently required for inspecting small cracks on express train wheels. This paper proposes an improved signal processing circuits, which uses the multiple amplifying circuits and the crack indicating pulse output system of the previous scan-type magnetic camera. Hall sensors are arrayed linearly, and the wheel is rotated with static speed in the vertical direction to sensor array direction. Each Hall voltages are amplified, converted and immediately operated by using, amplifying circuits, analog-to-digital converters and $\mu$-processor, respectively. The operated results, ${\partial}V_H/{\partial}t$, are compared with a standard value, which indicates a crack existence. If the ${\partial}V_H/{\partial}t$ is larger than standard value, the pulse signal is output, and indicates the existence of crack. The effectiveness of the novel method was verified by examine using cracks on the wheel specimen model.

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Development of 3-D Multi-Function Radar High-Speed Real-Time Signal Processor (3차원 다기능 레이더 고속 실시간 신호 처리기 개발)

  • Roh, Ji-Eun;Choi, Byung-Gwan;Lee, Hee-Young;Yang, Jin-Mo;Lee, Kwang-Chul;Lee, Dong-Hwi;Jung, Rae-Hyung;Kim, Tae-Hwan;Lee, Min-Joon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.12
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    • pp.1045-1059
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    • 2011
  • A 3-D multi-function radar(MFR) is a modern radar to provide various target information, such as range, doppler, and angle by performing surveillance, multiple target tracking, and missile guidance. In this paper, we introduced a real-time radar signal processor(RSP), which is a crucial component of MFR with its design, implementation using high-speed multiple DSP, and performance. Additionally, we verified that several advanced signal processing algorithms were well-performed in our RSP, such as MCA-CFAR algorithm for target detection in clutter environment, range and velocity measurement algorithm using discriminator estimation, and noise jammer detection algorithm using local minimum selection.

Development of High-Speed Real-Time Signal Processing Unit for Small Radio Frequency Tracking Radar Using TMS320C6678 (TMS320C6678을 적용한 소형 Radio Frequency 추적레이다용 고속 실시간 신호처리기 설계)

  • Kim, Hong-Rak;Hyun, Hyo-Young;Kim, Younjin;Woo, Seonkeol;Kim, Gwanghee
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.5
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    • pp.11-18
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    • 2021
  • The small radio frequency tracking radar is a tracking system with a radio frequency sensor that identifies a target through all-weather radio frequency signal processing for a target and searches, detects and tracks the target for the major target. In this paper, we describe the development of a board equipped with TMS320C6678 and XILINX FPGA (Field Programmable Gate Array), a high-speed multi-core DSP that acquires target information through all-weather radio frequency and identifies a target through real-time signal processing. We propose DSP-FPGA combination architecture for DSP and FPGA selection and signal processing, and also explain the design of SRIO for high-speed data transmission.

Sensorless control of the Next Generation High Speed Drive System in low speed region (차세대 고속전철 저속영역에서의 센서리스 제어)

  • Jin, Kang-Hwan;Suh, Yong-Hun;Lee, Sang-Hyun;Kim, Yoon-Ho
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.25 no.12
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    • pp.82-87
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    • 2011
  • In this paper, a sensorless speed control system is designed for the next generation high speed railway at zero and low speed region. The applied vector control scheme is a maximum torque per ampere(MTPA) method to utilize reluctance torque of IPMSM. The designed sensorless control scheme is a rotating high frequency voltage signal injection method. To verify the designed system, a simulator for the vector controller and sensorless controller is implemented using Matlab/simulink.

Implementation of Multiprocessor for Classification of High Speed OCR (고속 문자 인식기의 대분류용 다중 처리기의 구현)

  • 김형구;강선미;김덕진
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.6
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    • pp.10-16
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    • 1994
  • In case of off-line character recognition with statistical method, the character recognition speed for Korean or Chinese characters is slow since the amount of calculation is huge. To improve this problem, we seperate the recognition steps into several functional stages and implement them with hardwares for each stage so that all the stages can be processed with pipline structure. In accordance with temporal parallel processing, a high speed character recognition system can be implemented. In this paper, we implement a classification hardware, which is one of the several functional stages, to improve the speed by parallel structure with multiple DSPs(Digital Signal Processors). Also, it is designed to be able to expand DSP boards in parallel to make processing faster as much as we wish. We implement the hardware as an add-on board in IBM-PC, and the result of experiment is that it can process about 47-times and 71-times faster with 2 DSPs and 3 DSPs respectively than the IBM-PC(486D$\times$2-66MHz). The effectiveness is proved by developing a high speed OCR(Optical Character Recognizer).

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A Study on the Performance Elevation Methods of Next Generation Railway Freight Vehicles (한국형 고속열차를 이용한 고속선-기존선 연결구간의 속도향상 가능성에 관한 연구)

  • Ham Y.S.;Hong J.S.;Oh T.Y.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2005.10a
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    • pp.12-15
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    • 2005
  • In April 1, 2004, age of high-speed railway was opened to korea railroad. The railroad is a means of large transportation which has many talents such as a safety and a regularity. That is a results from various confidential performance tests and evaluations of the system. The railroad system consist of various subsystems - vehicle, power supply, signal, communications, track structures, operations, etc. Among them, as an item of safety evaluation there is a measurement of wheel/rail farce, so called a measurement of derailment coefficient. This is a very important item because a derailment of a train will bring about a big accident. Especially it is more important in high speed rail of which operation speed is over two times as fast as existing rail. In this paper, examined speed elevation possibility use the korean style high speed railway vehicle for reduce the running time of high-speed railway between high speed line and conventional line.

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