• Title/Summary/Keyword: High-speed serial display interface

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Design of 1/4-rate Clock and Date Recovery Circuit for High-speed Serial Display Interface (고속 직렬 디스플레이 인터페이스를 위한 1/4-rate 클록 데이터 복원회로 설계)

  • Jung, Ki-Sang;Kim, Kang-Jik;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.2
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    • pp.455-458
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    • 2011
  • 4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

Implementation of a Client Display Interface for Mobile Devices via Serial Transfer (모바일 직렬 전송방식의 클라이언트 디스플레이 인터페이스 구현)

  • Park Sang-Woo;Lee Yong-Hwan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.522-525
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    • 2006
  • Recently, mobile devices support multi-functions such as 3D game, wireless internet, moving pictures, DMB, GPS, and PMP. Bigger size of display device is indispensable to support these functions and higher speed of the interface is needed. However, conventional parallel interfaces between processor and display nodule are not competent enough for that high speed transfers. High-speed serial interface is beginning to appear as an alternative for parallel interface. The advantages of the serial interface are high bandwidth, small number of interconnections, low-power consumption, and good quality of electro-magnetic interference. In this paper, we implement serial interface and use it for a display module. LVDS is used for PHY layer and a defined packet is used for link layer. The feature of the implemented serial interface is the reduced number of interconnections with enough bandwidth.

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Implementation of High Speed Serial interface for testing LCD module by using the MDDI (MDDI방식 LCD모듈의 테스트하기 위한 고속직렬통신 인터페이스 구현)

  • Kim, Sang-Mok;Kang, Chang-Hun;Park, Jong-Sik
    • Proceedings of the KIEE Conference
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    • 2005.05a
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    • pp.212-214
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    • 2005
  • The MDDI(Mobile Digital Display Interface) standard is an optimized high-speed serial interconnection technology developed by Qualcomm and supports the VESA(Video Electronics Standard Association). It increases reliability and reduces power consumption in clamshell phones by decreasing the number of wires to interconnect with the LCD display. In this paper, the MDDI host is designed using VHDL and implemented on FPGA. We demonstrates that the MDDI host is connected with S3CA460 LCD controller is designed by Samsung Electronics Co. and display a steal image to the LCD.

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A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-${\mu}m$ CMOS

  • Moon, Yong-Hwan;Kim, Sang-Ho;Kim, Tae-Ho;Park, Hyung-Min;Kang, Jin-Ku
    • ETRI Journal
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    • v.34 no.1
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    • pp.35-43
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    • 2012
  • This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-${\mu}m$ CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

Advanced Mobile Display System Architecture

  • Kim, Chang-Sun;Kwon, Oh-Kyong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.850-853
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    • 2005
  • This paper presents issues of display hardware architecture, relating to memory, display driver IC architecture, and chip-to-chip interface. To achieve a low power and low cost mobile phone, not only the display architecture must be carefully selected, but also the driver-ICs optimized to accommodate the different modes of operation found in typical handheld devices. The technique of forming a photo sensor in each pixel using TFT and display module architecture are developed to add multi functions in display such as fingerprint recognition, image scanning, and integrated touch screen. Detailed architectures of IC partitioning, high-speed serial interface, D/A converter, and multi functions such as fingerprint recognition and image scanning using photo sensors are important to a power optimized system.

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An implementation of video transmission modes for MIPI DSI bridge IC (MIPI DSI 브릿지 IC의 비디오 전송모드 구현)

  • Seo, Chang-sue;Kim, Gyeong-hun;Shin, Kyung-wook;Lee, Yong-hwan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.291-292
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    • 2014
  • High-speed video transmission modes of master bridge IC are implemented, which supports MIPI (Mobile Industry Processor Interface) DSI (Display Serial Interface) standard. MIPI DSI master bridge IC sends RGB data and various commands to display module (slave) in order to test it. The master bridge IC consists of buffers storing video data of two lines, packet generation block, and D-PHY layer that distributes packets to data lanes and transmits them to slave. In addition, it supports four bpp (bit per pixel) formats and three transmission modes including Burst and Non-Burst (Sync Events, Sync Pulses types). The designed bridge IC is verified by RTL simulations showing that it functions correctly for various operating parameters.

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Low Power Design of a MIPI Digital D-PHY for the Mobile Signal Interface (모바일 기기 신호 인터페이스용 MIPI 디지털 D-PHY의 저전력 설계)

  • Kim, Yoo-Jin;Kim, Doo-Hwan;Kim, Seok-Man;Cho, Kyoung-Rok
    • The Journal of the Korea Contents Association
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    • v.10 no.12
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    • pp.10-17
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    • 2010
  • In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

Development of SDI Signal generator for Large size TFT-LCD (대형 TFT-LCD용 SDI 신호 생성기의 개발)

  • Choi, Dae-Seub;Sin, Ho-Chul
    • Journal of Satellite, Information and Communications
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    • v.9 no.1
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    • pp.13-16
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    • 2014
  • In applying LCD to TV application, one of the most significant factors to be improved is image sticking on the moving picture. LCD is different from CRT in the sense that it's continuous passive device, which holds images in entire frame period, while impulse type device generate image in very short time. To reduce image sticking problem related to hold type display mode, we made an experiment to drive TN-LCD like CRT. We made articulate images by fast refreshing images, and we realized the ratio of refresh time by counting between on time and off time for video signal input during 1 frame (16.7ms). Conventional driving signal cannot follow fast on-off speed, so we evaluated new signal generator using SDI (Serial Data Interface) mode signal generator. We realized articulate image generation similar to CRT by high fast full HD (High Definition) signals and TN-LCD overdriving. As a result, reduced image sticking phenomenon was validated by naked eye and response time measurement.

A Study on Manipulating Method of 3D Game in HMD Environment by using Eye Tracking (HMD(Head Mounted Display)에서 시선 추적을 통한 3차원 게임 조작 방법 연구)

  • Park, Kang-Ryoung;Lee, Eui-Chul
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.2
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    • pp.49-64
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    • 2008
  • Recently, many researches about making more comfortable input device based on gaze detection technology have been done in human computer interface. However, the system cost becomes high due to the complicated hardware and there is difficulty to use the gaze detection system due to the complicated user calibration procedure. In this paper, we propose a new gaze detection method based on the 2D analysis and a simple user calibration. Our method used a small USB (Universal Serial Bus) camera attached on a HMD (Head-Mounted Display), hot-mirror and IR (Infra-Red) light illuminator. Because the HMD is moved according to user's facial movement, we can implement the gaze detection system of which performance is not affected by facial movement. In addition, we apply our gaze detection system to 3D first person shooting game. From that, the gaze direction of game character is controlled by our gaze detection method and it can target the enemy character and shoot, which can increase the immersion and interest of game. Experimental results showed that the game and gaze detection system could be operated at real-time speed in one desktop computer and we could obtain the gaze detection accuracy of 0.88 degrees. In addition, we could know our gaze detection technology could replace the conventional mouse in the 3D first person shooting game.