• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.90-97
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• 2006

In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.12
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• pp.2921-2926
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• 2013

In this paper, a decimal floating-point arithmetic unit(DFP) was proposed and redesigned to support high speed arithmetic operation employed parallel processing technique. The basic architecture of the proposed DFP was based on the L.K.Wang's DFP and improved it enabling high speed operation by parallel processing for two operands with same size of exponent. The proposed DFP was synthesized as a target device of xc2vp30-7ff896 using Xilinx ISE and verified by simulation using Flowrian tool of System Centroid co. Compared to L.K.Wang's DFP and reference [6]'s method, the proposed DFP improved data processing speed about 8.4% and 3% respectively in case of same input data.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.951-956
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• 2007

This paper suggests a high-speed control method which is suitable for multi-joint robots using a real-time stand-alone controller for general-purpose. The fast processing controller consists of a PCI Interface Board and 2-axe PWM drivers. The PCI Interface Board consists of 32-channel PWM output ports, 32-channel Encoder Counters, 32-channel A/D Converters and 48-channel Digital I/O ports, and all the I/O data transmissions are completed within 1ms. And The 2-axe PWM driver can be redesigned easily in order to embed in each link. Experimental implementations show that the high-speed control method can be used for the real-time control which is essential to controlling of multi-body robots such as humanoid robots. Especially, it is efficient for realizing the model-based motion control in demand of much calculation time by the high I/O communication speed.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.05a
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• pp.657-662
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• 2004

This paper presented is a case study of a real compressor rotor of a refinery plant for high speed balancing of flexible rotor. The rotor was tested in the expert high-speed balancing facility established by KIMM at early 2004. The capability of the facility can reach 40000rpm in rotation speed and 8 ton in rotor weight for high-speed balancing. The facility performs multi-plane at-speed balancing using influence coefficient from the vibration data measured at two pedestals. The test rotor had exceeded permissible criteria of vibration at initial run. But by processing a low-speed balancing at 1000 rpm and six trial run trying to calculate influence coefficient of rotor to the range of operating speed, the final result of high-speed balancing revealed a remarkable reduce of vibration at pedestal of the rotor.

• Publications of The Korean Astronomical Society
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• v.23 no.2
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• pp.91-107
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• 2008

In this paper, we introduce the performance evaluation and development of Raw VLBI Data Buffer(RVDB) system for the synchronized playback processing of observed data in Korea-Japan Joint VLBI Correlator(KJJVC). The high-speed correlation processing system is under development so that the radio data obtained with 8192 channels and 8 Gbps speed from 16 stations will be able to be processed. When the recorded data of each station are played to correlator, the time synchronization of each station is very important because the correlator should process the data obtained with same time and condition. There are many types of recorder systems in the East Asia VLBI Network (EAVN). Therefore it is required to prepare the special time synchronized playback processing system to synchronize the time tag of observed data. The developed RVDB system consists of Data Input Output(DIO), 10GbE switch, and Disk Data Buffer(DDB). It can record the data with maximum 2 Gbps speed, and can play back the data to correlator with nominal 2 Gbps speed. To enable to play back the data of different playback system to the correlator, we developed the high-speed time synchronized playback processing system. We carried out the experiments of playing back and correlation for gigabit correlator and VCS trial product so as to confirm the performance of developed time synchronized playback processing system. In case of online and offline playing back experiment for gigabit correlator, we confirmed that the online and offline correlation results were the same. In case of playing back experiment for VCS trial product, we verified that the wide band and narrow band correlation results were also the same. Through the playing back experiments of RVDB system, the effectiveness of developed RVDB system was verified. In this paper, the system design, construction and experimental results are shown briefly.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.389-390
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• 2012

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Bulletin of the Korean Space Science Society
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• 2008.10a
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• pp.37.2-37.2
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• 2008

Korea-Japan Joint VLBI Correlator (KJJVC), to be used for Korean VLBI Network (KVN) in Korea Astronomy & Space Science Institute (KASI), is a high-speed calculator that outputs the correlation results in the maximum speed of 1.4GB/sec.To receive and record this data keeping up with this speed and with no loss, the design of the software running on the data archive system for receving and recording the output data from the correlator is very important. But, the simple kind of programming using just single thread that receives data from network and records it by turns, can cause a bottleneck effect while processing high speed data and a probable data loss, and cannot utilize the merit of hardwares supporting multi core or hyper threading, or operating systems supporting these hardwares. In this talk we summarize the design of the data transfer software for KJJVC and high speed, large capacity data archive system using general socket programming and multi threading techniques, and the pre-BMT(Bench Marking Test) results from the tests of the storage product providers' proposals using this software.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.3
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• pp.7-12
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• 2012

Ceramic core processing technology using 5-axis high-speed cutting machine is applied to make the glass molds for aspherical ophthalmic lenses. In the technology, optimum processing conditions for aspherical ceramic molds are based on minimal experimental data of surface roughness. Such surface roughness is influenced by fabricating tools, cutting speed, feed rate, and depth of cut, respectively. In this paper, we present that surface roughness and shape accuracy of aspheric ceramic mold obtained by optimum processing conditions are Pa $0.6184{\mu}m$ and Pt $5.0301{\mu}m$, respectively, and propose that these values are sufficiently possible to apply to making the glass molds for aspherical ophthalmic lenses.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.8-18
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• 1993

A multi-font, multi-size and high speed character recognition system is designed. The design principles are simpilcity of algorithm, adaptibility, learnability, hierachical data processing and attention by feed back. For the multi-size character recognition, the extracted character images are normalized. A hierachical classifier classifies the feature vectors. Feature is extracted by applying the directional receptive field after the directional dege filter processing. The hierachical classifier is consist of two pre-classifiers and one decision making classifier. The effect of two pre-classifiers is prediction to the final decision making classifier. With the pre-classifiers, the time to compute the distance of the final classifier is reduced. Recognition rate is 95% for the three documents printed in three kinds of fonts, total 1,700 characters. For high speed implemention, a multiprocessor system with the ring structure of four transputers is implemented, and the recognition speed of 30 characters per second is aquired.