• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.3
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• pp.257-265
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• 2016

In this study, an optimal design for motor-driven track type traveling system applied into high clearance working machineries in orchard is proposed. Tractive performance and hill climbing ability were predicted and evaluated for the optimal motor traveling system by taking into account of soil characteristics in orchard utilizing the high clearance working machineries. Design criteria for tractive performance were based on the traction force calculated from tractive effort subtracted by motion resistance, while hill climbing ability had its design criteria that fulfill the climbing 20% slope ground at a speed of 3km/h. Based on the evaluation results of traction and climbing ability, two DC48V, 4500rpm, 1.6kW AC motors were independently applied to both left and right side of orbits; each motor is designed to transmit power on driving sprocket of track type traveling system via 50:1 reduction gear ratio. The motor-driven track type traveling system developed in the study found to have 396 kgf of tractive force, which is 12.5% higher than climbing resistance at orchard soil having 20% slope ground (352 kgf), demonstrating sufficient tractive performance and hill climbing ability.

• KEPCO Journal on Electric Power and Energy
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• v.6 no.2
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• pp.173-179
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• 2020

Electric vehicles (EVs) using lithium secondary batteries (LIBs) with excellent power and long-term cycle performance are gaining interest as the successors of internal combustion engine (ICE) vehicles. However, there are few systematic researches for fast charging to satisfy customers' needs. In this study, we compare the degradation of LIB where its composition is LiNi_0.5Co_0.2Mn_0.3/Graphite with the constant current and constant power-charging method. The charging speed was set to 1C, 2C, 3C and 4C in the constant current mode and the value of constant power was calculated based on the energy at each charging speed. Therefore, by analyzing the battery degradation based on the same charging energy but different charging method; CP charging method can slow down the battery degradation at a high rate of 3C through the voltage curve, capacity retention and DC-IR. However, when the charging rate was increased by 4C or more, the deviation between the LIBs dominated the degradation than the charging method.

• Resources Recycling
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• v.3 no.2
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• pp.28-34
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• 1994

A part of used cables, such as electric and communication cables has already been recycled by using simple processing methods. However, it has been found that the main problems in recycling of the used cables are insufficient treatment of fine stranded wires and low recovery of copper by air separation process. It has been shown that copper can be effectively separated from the PE using a solvent treatment method. In the present study, the used communication wires having diameter of 0.4 mm are treated in the mixing solution of toluene and water at $86^{\circ}C$ for about 10 minutes. In the solvent treatment, the copper wires recovered have 10~15mm length, which are much longer than that of 1~2mm length copper wires recovered by air table concentration method used in current recycling plants. The process consisting of cutting, air separation and electrostatic separation would be recommendable for the treatment of mixed cables. In this investigation, fine copper powders can also efficiently be recovered from insulation materials using electrostatic separator at the conditions of 20~50RPM roller speed and 15~30KV high DC power.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.659-666
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• 2006

Servo-motors are used as key components of automated system by performing precise motion control as accurate positioning and accurate speed regulation in response to the commands from computers and sensors. Especially, the linear brushless servo-motors have numerous advantages over the rotary servo motors which have connection with the friction induced transfer mechanism such as ball screws, timing belts, rack/pinion. This paper proposes an estimation method of unknown motor system parameters using the informations from the sinusoidal driving type linear brushless DC motor dynamics and outputs. The estimated parameters can be used to tune the controller gain and a disturbance observer. In order to meet this purpose high performance Digital Signal Processor, TMS320F240, designed originally for implementation of a Field Oriented Control(FOC) technology is adopted as a controller of the liner BLDC servo motor. Having A/D converters, PWM generators, rich I/O port internally, this servo motor application specific DSP play an important role in servo motor controller. This linear BLDC servo motor system also contains IPM(Intelligent Power Module) driver and hail sensor type current sensor module, photocoupler module for isolation of gate signals and fault signals.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.388-388
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• 2016

Chemical mist deposition (CMD) of poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) was investigated with cavitation frequency f, solvent, flow rate of nitrogen, substrate temperature $T_s$, and substrate dc bias $V_s$ as variables for efficient PEDOT:PSS/crystalline (c-)Si heterojunction solar cells (Fig. 1). The high-speed camera and differential mobility analysis characterizations revealed that average size and flux of PEDOT:PSS mist depend on f, solvent, and $V_s$. The size distribution of mist particles including EG/DI water cosolvent is also shown at three different $V_s$ of 0, 1.5, and 5 kV for a f of 3 MHz (Fig. 2). The size distribution of EG/DI water mist without PEDOT:PSS is also shown at the bottom. A peak maximum shifted from 300-350 to 20-30 nm with a narrow band width of ~150 nm for PEDOT:PSS solution, whose maximum number density increased significantly up to 8000/cc with increasing $V_s$. On the other hand, for EG/water cosolvent mist alone, the peak maximum was observed at a 72.3 nm with a number density of ~700/cc and a band width of ~160 nm and it decreased markedly with increasing $V_s$. These findings were not observed for PEDOT:PSS/EG/DI water mist. In addition, the Mie scattering image of PEDOT:PSS mist under white bias light was not observed at $V_s$ above 5 kV, because the average size of mist became smaller. These results imply that most of solvent is solvated in PEDOT:PSS molecule and/or solvent is vaporized. Thus, higher f and $V_s$ generate preferentially fine mist particle with a narrower band width. Film deposition occurred when $V_s$ was impressed on positive to a c-Si substrate at a Ts of $30-40^{\circ}C$, whereas no deposition of films occurred on negative, implying that negatively charged mist mainly provide the film deposition. The uniform deposition of PEDOT:PSS films occurred on textured c-Si(100) substrate by adjusting $T_s$ and $V_s$. The adhesion of CMD PEDOT:PSS to c-Si enhanced by $V_s$ conspicuously compared to that of spin-coated film. The CMD PEDOT:PSS/c-Si solar cell devices on textured c-Si(100) exhibited a ${\eta}$ of 11.0% with the better uniformity of the solar cell parameters. Furthermore, ${\eta}$ increased to 12.5% with a $J_{sc}$ of $35.6mA/cm^2$, a $V_{oc}$ of 0.53 V, and a FF of 0.67 with an antireflection (AR) coating layer of 20-nm-thick CMD molybdenum oxide $MoO_x$ (n= 2.1) using negatively charged mist of 0.1 wt% 12 Molybdo (VI) phosphoric acid n-Hydrate) $H_3(PMo_{12}O_40){\cdot}nH_2O$ in methanol. CMD. These findings suggest that the CMD with negatively charged mist has a great potential for the uniform deposition of organic and inorganic on textured c-Si substrate by adjusting $T_s$ and $V_s$.