• Korean Journal of Optics and Photonics
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• v.33 no.3
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• pp.99-105
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• 2022

We have evaluated the performance of an all-optical automatic gain-controlled (AGC) erbium-doped fiber amplifier (EDFA) to suppress the optical signal fluctuation induced by atmospheric turbulence in terrestrial free-space optical communication systems. In our measurements, the input power into the EDFA was set to be -30 dBm and -10 dBm to operate the amplifier in the small-signal and saturation regions, respectively. The fluctuations in the optical signal were emulated with an acousto-optic modulator driven with a sinusoidal voltage. From the measured results, we have found that an all-optical AGC EDFA could suppress the optical signal fluctuation effectively, as long as the EDFA operated in the small-signal region with a high feedback amplified spontaneous emission (ASE) power.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1059-1066
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• 2005

This paper reports an application of Doherty amplifier for efficiency improvement of feedforward power amplifier(FPA). For performance analysis, we measured 15 W average output power using WCDMA 4FA input signal with a center frequency 2.14 GHz. The applied Doherty amplifier presents the characteristics of high efficiency and low linearity in comparison to the class AB amplifier, and it was used as main amplifier of FPA fir efficiency improvement. To analyze the change of characteristic, tow Doherty amplifiers whose linearity and efficiency are different were applied. The applied FPAs are improved about $2\%$ or more performance in efficiency, but decreased in linearity on 15 W average output power. We additionally modified the coupling factor(CF) of the error loop and the error amplifier capacity for linearity improvement. Aa a result, the efficiency improvement and high linearity resulted from the change of CF and error amplifier capacity. However, we think if the linearity of Doherty amplifier were more than 35 dBc, the FPA would improve the performance about $2\%$ or more efficiency and maintain enough linearity.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of Navigation and Port Research
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• v.27 no.4
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• pp.443-447
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• 2003

In this work. using 0.2 GaAs modulation doped FET(MODFET), a high performance DBS downconverter MMIC was developed for direct broadcasting satellite (DBS) application. Without LNA, the downconverter MMIC showed a very low noise of 4.8 dB, which is lower by 3 dB than conventional ones. A low LO power of -10 dBm was required for the normal DBS operation of the downconverter MMIC. which reduced the power consumption via a removal of LO amplifier on MMIC. It required only a low power consumption of 175 mW, which is lower than 70 percent of conventional ones. The LO leakage power at IF output was suppressed to a lower level than 30 dBm, which removes a bulky LO rejection filter on a board. The fabricated chip, which include a mixer, If amplifiers. LO rejection filter, and active balun, exhibited a small size of $0.84{\times}0.9\textrm{mm}^2$.

• Journal of Radiation Protection and Research
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• v.41 no.2
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• pp.81-86
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• 2016

Background: For positron emission tomography (PET) application, cadmium zinc telluride (CZT) has been investigated by several institutes to replace detectors from a conventional system using photomultipliers or Silicon-photomultipliers (SiPMs). The spatial and energy resolution in using CZT can be superior to current scintillator-based state-of-the-art PET detectors. CZT has been under development for several years at the Korea Atomic Energy Research Institute (KAERI) to provide a high performance gamma ray detection, which needs a single crystallinity, a good uniformity, a high stopping power, and a wide band gap. Materials and Methods: Before applying our own grown CZT detectors in the prototype PET system, we investigated preliminary research with a developed discrete type data acquisition (DAQ) system for coincident events at 128 anode pixels and two common cathodes of two CZT detectors from Redlen. Each detector has a $19.4{\times}19.4{\times}6mm^3$ volume size with a 2.2 mm anode pixel pitch. Discrete amplifiers consist of a preamplifier with a gain of $8mV{\cdot}fC^{-1}$ and noise of 55 equivalent noise charge (ENC), a $CR-RC^4$ shaping amplifier with a $5{\mu}s$ peak time, and an analog-to-digital converter (ADC) driver. The DAQ system has 65 mega-sample per second flash ADC, a self and external trigger, and a USB 3.0 interface. Results and Discussion: Characteristics such as the current-to-voltage curve, energy resolution, and electron mobility life-time products for CZT detectors are investigated. In addition, preliminary results of gamma ray imaging using 511 keV of a $^{22}Na$ gamma ray source were obtained. Conclusion: In this study, the DAQ system with a CZT radiation sensor was successfully developed and a PET image was acquired by two sets of the developed DAQ system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.353-353
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• 2008

Carbon nanotubes (CNTs) are attractive for field emitter because of their outstanding electrical, mechanical, and chemical properties. Several applications using CNTs as field emitters have been demonstrated such as field emission display (FED), backlight unit (BLU), and X-ray source. In this study, we fabricated a CNT cathode using transparent ultra-thin CNT film. First, CNT aqueous solution was prepared by ultrasonically dispersing purified single-walled carbon nanotubes (SWCNTs) in deionized water with sodium dodecyl sulfate (SDS). To obtain the CNT film, the CNT solution in a milliliter or even several tens of micro-litters was deposited onto a porous alumina membrane through vacuum filtration process. Thereafter, the alumina membrane was solvated by the 3 M NaOH solution and the floating CNT film was easily transferred to an indium-tin-oxide (ITO) glass substrate of $0.5\times0.5cm^2$ with a film mask. The transmittance of as-prepared ultra-thin CNT films measured by UV-Vis spectrophotometer was 68~97%, depending on the amount of CNTs dispersed in an aqueous solution. Roller activation, which is a essential process to improve the field emission characteristics of CNT films, increased the UV-Vis transmittance up to 93~98%. This study presents SEM morphology of CNT emitters and their field emission properties according to the concentration of CNTs in an aqueous solutions. Since the ultra-thin CNT emitters prepared from the solutions show a high peak current density of field emission comparable to that of the paste-base CNT emitters and do not contain outgassing sources such as organic binders, they are considered to be very promising for small-size-but-high-end applications including X-ray sources and microwave power amplifiers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.813-822
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• 2009

We have investigated operation of a 1:2:2 asymmetric 3-stage Doherty PA(Power Amplifier) and implemented using the Freescale's 4 W, 10 W PEP LDMOSFETS at 1 GHz. By employing the three peak efficiency characteristics, compared to the two peak N-way Doherty PA, the asymmetric 3-stage Doherty can overcome the serious efficiency degradation along the backed-off output power region and maximize the average efficiency for the modulation signal. To maximize the efficiency characteristic, the inverse class F PA has been designed as carrier and peaking amplifiers. Furthermore, to extract the proper load modulation operation, the adaptive gate bias control signal has been applied to the two peaking PAs based on the envelope tracking technique. For the 802.16e Mobile WiMAX(World Interoperability for Microwave Access) signal with 8.5 dB PAPR(Peak to Average Power Ratio), the proposed Doherty PA has shown 55.46 % of high efficiency at an average output power of 36.85 dBm while maintaining the -37.23 dB of excellent RCE(Relative Constellation Error) characteristic. This is the first time demonstration of applying the saturated PA and adaptive gate bias control technique to the asymmetric 3-stage Doherty PA for the highly efficient transmitter of the base-station application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.69-76
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• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.