• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.7
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• pp.63-73
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• 2004

This paper proposes an efficient centralized sin91e buffer management algorithm to arbitrate access contention mon processors on the multi-processor system for high-speed Packet filtering and proves that the algorithm provides reasonable performance by implementing it and applying it to a real multi-processor system. The multi-processor system for parallel packet filtering is modeled based on a network processor to distribute the packet filtering rules throughout the processors to speed up the filtering. In this paper we changed the number of processors and the processing time of the filtering rules as variables and measured the packet transfer rates to investigate the performance of the proposed algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.473-480
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• 2021

To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, the column-wise multiplication algorithm is optimized with the primitive instruction of RISC-V processor, which improved the performance of 256-bit and 512-bit multiplication by 19% and 8% than previous works, respectively. Lastly, we suggest the instruction extension for the high-speed multiplication on the RISC-V processor.

• The KIPS Transactions:PartA
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• v.18A no.2
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• pp.45-52
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• 2011

In the past, a patient went to the room where an ultrasound image diagnosis device was set, and then he or she was examined by a doctor. However, currently a doctor can go and examine the patient with a handheld ultrasound device who stays in a room. However, it was implemented with only fundamental functions, and can not meet the high performance required by the focusing algorithm of ultrasound beam which determines the quality of ultrasound image. In addition, low energy consumption was satisfied for the mobile ultrasound device. To satisfy these requirements, this paper proposes a high-performance and low-power single instruction, multiple data (SIMD) based multi-core processor that supports a representative beamforming algorithm out of several focusing methods of mobile ultrasound image signals. The proposed SIMD multi-core processor, which consists of 16 processing elements (PEs), satisfies the high-performance required by the beamforming algorithm by exploiting considerable data-level parallelism inherent in the echo image data of ultrasound. Experimental results showed that the proposed multi-core processor outperforms a commercial high-performance processor, TI DSP C6416, in terms of execution time (15.8 times better), energy efficiency (6.9 times better), and area efficiency (10 times better).

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.3
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• pp.77-85
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• 2009

Execution times of tasks can be variable depend on input data. If we choose a high performance processor to satisfy the worst case execution times, the hard cost becomes high and the energy consumption also becomes large. To apply a lower performance processor, we have to utilize processor capacity maximally while overrunning tasks can not affect deadlines of other tasks. To be used for such systems, this paper presents SBP (Shared Bandwidth Partitioning) that a processor bandwidth is reserved and shared among all tasks. If a task needs more processor capacity, it can use a portion of the shared bandwidth. A simulation result shows that SBP provides better performance than previous algorithms. SBP reduces deadline miss ratio which is related to scheduling quality. And the number of context switches, which is related to system overhead, is also reduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1071-1074
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• 2002

In this paper, power quality analysis system is proposed where voltage or current waveforms are nonsinusoidal. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the input signal. The proposed system is based on FFT processor which is designed using VHDL(Very high-speed integrated circuit Hardware Description Language). In the design of FFT processor, radix- $2^2$ is adopted to reduce several complex multipliers for twiddle factor. Complex multiplier is implemented as only shifters and adders. Therefore, the system is able to have both high hardware efficiency and high performance.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.251-256
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• 2017

Recently, multicore processor system is widely adopted not only in general purpose computers but also in embedded systems and mobile devices in order to improve performance. Since the power dissipation issue of multicore processor system is very significant, it must be estimated accurately in the early design stage. In this paper, a fast power analysis tool for a high performance multicore processor based on the trace-driven simulator has been developed. To achieve it, the power dissipation of each hardware unit per core are added. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation per instruction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.515-520
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• 1998

In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.526-531
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• 2009

In this paper, we propose new novel technique (ILCT: Instruction-Level Correlation Technique) which can detect tempered instructions by software attacks or hardware attacks before their execution. In conventional works, due to both high complex computation of cipher process and low processing speed of cipher modules, existing secure processor architecture applying cipher technique can cause serious performance degradation. While, the secure processor architecture applying ILCT with FEC does not incur excessive performance decrease by complexity of computation and speed of tampering detection modules. According to experimental results, total memory overhead including parity are increased in average of 26.62%. Also, secure programs incur CPI degradation in average of $1.20%{\sim}1.97%$.