• Journal of KIISE
• /
• v.42 no.10
• /
• pp.1280-1285
• /
• 2015

Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression processors such as ReCPU and SMPU perform pattern matching in a similar approach to that used in general purpose processors, which provide the flexibility when updating patterns. However, these processors are inefficient in performing class matching since they do not provide character class matching capabilities. This paper proposes an instruction set and architecture of a regular expression matching processor, which can support character class matching. The proposed processor can efficiently perform character class matching since it includes character class, character range, and negated character class matching capabilities.

• 한국신재생에너지학회:학술대회논문집
• /
• 2006.11a
• /
• pp.451-454
• /
• 2006

WGS reaction over Mo2C and ceria based catalysts was investigated to develop an alternative commercial Cu-Zn/Al2O3 catalyst for fuel processor and hydrogen station. The Mo2C catalysts were prepared by a temperature programmed method and the various metal supported cerium oxide catalysts were prepared by an Impregnation method. The catalysts were characterized by the N2 physisorption, Co chemisorption, XRD, TEM and TPR. It was found that Mo2C and 0.2wt% Pt-40wt%, Ni/CeO2 catalysts had higher activity and stability than the Cu-Zn/Al203 above $260^{\circ}C$. Moreover, CO conversion of more than 85% was observed at $280{\sim}300^{\circ}C$. But all catalysts were deactivated during the thermal cycling runs. The results suggest that these catalysts are an attractive candidate for the alternative Cu-Zn/Al2O3 catalyst for fuel processor and hydrogen station applications.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.12
• /
• pp.3144-3153
• /
• 1996

ATM switching system is made up of transport network and control newrk according to its functions. The control device, basic part of control network must be developed before developing any other functions, and control device must be stable and need high reliability. Out distributed ATM switching system consists of several ALSs that provides variable local call services, and an ACS that interconnect among several ALSs. Eech ALS has CCCP that takes charage of call and connection control functions, and ACS has an OMP that takes charge of OA&M(Operation, Administration and Maintenance) functios. In this paper, we analyzed the performance evaluation of control device that manipulate subscriber's call based on ITU-T Q.2931 standard protocol messages and Interprocessor communication messages. As a result of simulation when the number of ALS is under 22, as the call arrival rate increase the processor utilization of CCCP increase rapidly than that of OMP. When the number of ALS is incremented to 22, the processor utilization of CCCP is balanced with the of OMP, and when the number of ALS exceeds 22, the processor utiliztion of OMP increase rapidly. Also if messary processing time of OMP is 1.35 times that of CCCP, processor utilizations of CCCP and OMP is equal.

• Proceedings of the KIEE Conference
• /
• 1992.07b
• /
• pp.1032-1034
• /
• 1992

There are increasing demands for the Space Power System to get more useful performance. These demands are high-efficiency, high-confidency, light-weight, small-size, and the systems's flexibility which can shorten the development time. These demands can be achieved when we make the use of $\mu$-Processor. This paper, therefore, shows an analysis and experimental results for the Space Power System with MC 68000, Motorola's 16 bits MPU, to find the system's characteristics.

• Journal of the Korean Society for Precision Engineering
• /
• v.19 no.8
• /
• pp.155-160
• /
• 2002

In this paper, a controller design for brushless linear motor is implemented. The designed controller is mainly composed of current, speed and position controller, which are carried out by the high-speed digital signal processor (DSP). In addition the PWM inverter is controlled by space voltage PWM method. This system is implemented by using 32-bit DSP (TMS320C31), a high-integrated logic device (EPM7192), and IPM (Intelligent Power Module) for compact and powerful system design. The experimental results show the effective performance of controller for the brushless linear motor.

• Proceedings of the KOSOMBE Conference
• /
• v.1997 no.05
• /
• pp.342-344
• /
• 1997

Owing to technical advances in very large-scale integrated circuits (VLSI), high-speed digital signal processing (DSP) chips become fast enough to allow for real-time implementation of hearing aid algorithms in units small enough to be wearable. In this paper, we present a digital hearing aid processor (DHAP) chip built around a general-purpose 16-bit DSP core. The designed DHAP performs a nonlinear loudness correction of 8 octave frequency bands based on audiometric measurements. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the has a low power feature and $5.410\times5.720mm^2$ dimensions that fit for wearable devices.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.12
• /
• pp.110-119
• /
• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.114-117
• /
• 2002

The airborne tracking radar is located in front of aircraft or missile and measures and tracks a target motion. The signal processor receives target signals from a receiver using A/D converters, and calculates the target motion, and transfers the data to the aircraft or missile control unit. Since the signal processing system is required to be lightweight and small size as well as high performance to calculate and analyze the received signal, we use high speed DSPs and SMD type components having low power consumption. In this paper, we describe the design concept of signal processing system of the airborne tracking radar.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.50 no.6
• /
• pp.266-271
• /
• 2001

In this paper, a controller design for coreless linear synchronous motor is proposed. The designed controller is mainly composed of speed and current control, which are carried out by the high-speed digital signal processor(DSP). In addition the PWM inverter is controlled by space voltage PWM method. This system is implemented using by 32-bit DSP(TMS320C31), a high-integrated logic device(EPM940), and IPM(Intelligent Power Modules) for compact and powerful system design. The experimental results show the effective performance of controller for coreless linear synchronous motor.

• ETRI Journal
• /
• v.10 no.3
• /
• pp.49-61
• /
• 1988

HARP(High-performance Architecture for Risc-type Processor)는 한국전자통신연구소에서 정의한 고유모델의 RISC형 32비트 CPU이다. HACAM(HArp CAche and Mmu)은 HARP의 캐쉬 메모리 및 MMU(Memory Management Unit)를 custom IC로 구현한 VLSI 칩이다. 본 논문에서는 HACAM의 구조 설계에 대해 메모리 구조 및 메모리 관리 방식, 캐쉬 메모리 및 HACAM의 구성 등으로 나누어 설명하고 그 타당성을 논하였다.