• Title/Summary/Keyword: High-performance processor

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VHDL Module Implementation of High-speed Wireless Modem using Direct Sequence Spread Spectrum Communication Method

  • Lee, Jung-Ha;Kim, Il-Hwan
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.113.3-113
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    • 2001
  • In this paper, we have designed the VHDL module of DS/SS QPSK wireless modem processor for digital data communication. The spread spectrum method is used for modern processor, because this method guarantees good frequency efficiency and higher security. Also, it guarantees good performance in digital communication system under multi-path interferences. The differential encoder and decoder are used for simple circuit composition in the signal detection. For the synchronization of receiver, matched filter and power detector are used. And the IF modulation/demodulation of QPSK method is used in the digital level. The transmitter of VHDL modem processor consists of differential encoder, PN code generator, and QPSK ...

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A Study on the communication Method between the Adjacent Processors (근접한 프로세서간 통신방식에 관한 연구)

  • 황대환;박영덕;김선형;조규섭;박병철
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.12 no.6
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    • pp.599-606
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    • 1987
  • Giving a high degree of intelligence to the electronic equipments such as communication system is the general trend of nowadays. Therefore the multi-processor will be required in a single system and the switch gives an example of it. In this paper, "Reserved Bus" is proposed as the interprocessor communication method applicable to such system which has multi-processor in the limited space. The performance of proposed method is also analyzed. analyzed.

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Fuzzy Control of Computer Automatic System with Color Matching and Dispensing Functions (칼라 맞춤 및 분배 기능을 가진 컴퓨터 자동화 시스템의 퍼지 제어)

  • 한일석;류상문;임태우;안태천
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2000.05a
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    • pp.146-149
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    • 2000
  • In this paper, Computer Colour Matching and Kitchen System (CCMKS) is developed on the basis of delphi package and one-chip processor with fuzzy-PID control. CCMKS will be widely used in the colour dyeing industry as an integrated colour matching and dispensing system which have more advantages than the conventional matching or dispensing system, when controlling the real dyeing processes. Delphi is utilized in making database and search/matching routes. The developed matching function reduces the search and matching time to about one third. One-chip processor is designed and manufactured for the distributed control of three-phase induction motors. Fuzzy-PID control is applied to the speed control of three-phase induction motors for a very precise weight of colour at CCMKS. The developed kitchen function decreases the dispensing time to about one twentieth. The experimental results show CCMKS has more excellent search time, more precise weight and much high fidelity than conventional colour matching or dispensing system, in the performance.

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Implementation of GA Processor with Multiple Operators, Based on Subpopulation Architecture (분할구조 기반의 다기능 연산 유전자 알고리즘 프로세서의 구현)

  • Cho Min-Sok;Chung Duck-Jin
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.5
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    • pp.295-304
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    • 2003
  • In this paper, we proposed a hardware-oriented Genetic Algorithm Processor(GAP) based on subpopulation architecture for high-performance convergence and reducing computation time. The proposed architecture was applied to enhancing population diversity for correspondence to premature convergence. In addition, the crossover operator selection and linear ranking subpop selection were newly employed for efficient exploration. As stochastic search space selection through linear ranking and suitable genetic operator selection with respect to the convergence state of each subpopulation was used, the elapsed time of searching optimal solution was shortened. In the experiments, the computation speed was increased by over $10\%$ compared to survival-based GA and Modified-tournament GA. Especially, increased by over $20\%$ in the multi-modal function. The proposed Subpop GA processor was implemented on FPGA device APEX EP20K600EBC652-3 of AGENT 2000 design kit.

Design of the Ground Resistance Measuring System using high Performance Filter System (고성능 필터를 이용한 접지저항 측정시스템의 설계)

  • 이기홍;정재기;주형준
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.15 no.6
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    • pp.43-48
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    • 2001
  • This paper represents the design of the ground resistance measuring system insensitive to the noise in the earth. Generally, conventional ground resistance measuring instruments may fail to give a precise values for ground resistance under the situations where there is a high ground potential produced by unbalanced power system currents, haromonic currents and noise etc. To make up the defect of conventional ground resistance measuring instruments, in this paper the ground resistance measuring system using high-performance L-C resonant filter and digital signal processor is designed and the insentivity of the designed ground resistance measuring system for noise in the earth is verified by field test on power service and off power service.

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Mileage-based Asymmetric Multi-core Scheduling for Mobile Devices (모바일 디바이스를 위한 마일리지 기반 비대칭 멀티코어 스케줄링)

  • Lee, Se Won;Lee, Byoung-Hoon;Lim, Sung-Hwa
    • Journal of Korea Society of Industrial Information Systems
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    • v.26 no.5
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    • pp.11-19
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    • 2021
  • In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

A Study on the Verification Platform Architecture for MPSoC (MPSoC 검증 플랫폼 구조에 관한 연구)

  • Song, Tae-Hoon;Song, Moon-Vin;Oh, Chae-Gon;Chung, Yun-Mo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.8
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    • pp.74-79
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    • 2007
  • In general, the high cost, long time, and complex steps are required in the design and implementation of MPSoC(Multi-Processor System on a Chip), therefore a platform is used to test the functionality and performance of IPs(Intellectual Properties). In this paper, we study a platform architecture to verify IPs based on Interconnect Network among processors, and show that the MPSoC platform gives better performance than a single processor for an application program.

Implementation and Performance Evaluation of the Dual Controller System for Precision Control of Gripper (그리퍼 정밀 제어를 위한 이중 제어기 시스템의 구현 및 성능 평가)

  • Lee, Seung-Yong;Ham, Un-Hyong;Park, Young-Woo;Jung, Il-Kyun;Lim, Sun
    • The Journal of Korea Robotics Society
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    • v.13 no.1
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    • pp.72-78
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    • 2018
  • This paper proposes a Dual Controller System for Precision Control (DCSPC) for control of the gripper. The DCSPC consists of two subsystems, CDSP (Controller based DSP) and CARM (Controller based ARM processor). The CDSP is developed on a DSP processor and controls the gripping motor and LVDT. In particular, the CARM is implemented using Linux and ARM processor according to recent research related to open-source. The robot for high-precision assembly is divided into the robot control and the gripper control section and controls CARM and CDSP systems respectively. In this paper, we also proposed and measured the performance of communication API. As a result, it is expected to recognize improvements in communication between CARM and the robot controller, and will continue to conduct relevant research among other commercial robot controllers.

Using the On-Package Memory of Manycore Processor for Improving Performance of MPI Intra-Node Communication (MPI 노드 내 통신 성능 향상을 위한 매니코어 프로세서의 온-패키지 메모리 활용)

  • Cho, Joong-Yeon;Jin, Hyun-Wook;Nam, Dukyun
    • Journal of KIISE
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    • v.44 no.2
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    • pp.124-131
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    • 2017
  • The emerging next-generation manycore processors for high-performance computing are equipped with a high-bandwidth on-package memory along with the traditional host memory. The Multi-Channel DRAM (MCDRAM), for example, is the on-package memory of the Intel Xeon Phi Knights Landing (KNL) processor, and theoretically provides a four-times-higher bandwidth than the conventional DDR4 memory. In this paper, we suggest a mechanism to exploit MCDRAM for improving the performance of MPI intra-node communication. The experiment results show that the MPI intra-node communication performance can be improved by up to 272 % compared with the case where the DDR4 is utilized. Moreover, we analyze not only the performance impact of different MCDRAM-utilization mechanisms, but also that of core affinity for processes.

Design and Implementation of an InfiniBand System Interconnect for High-Performance Cluster Systems (고성능 클러스터 시스템을 위한 인피니밴드 시스템 연결망의 설계 및 구현)

  • Mo, Sang-Man;Park, Kyung;Kim, Sung-Nam;Kim, Myung-Jun;Im, Ki-Wook
    • The KIPS Transactions:PartA
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    • v.10A no.4
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    • pp.389-396
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    • 2003
  • InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18${\mu}{\textrm}{m}$ CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.