• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.263-263
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• 2012

본 연구는 실리콘 표면에 형성된 pyramid 구조의 크기와 각도, aspect ratio에 따른 반사도, 흡수율 최적화에 관한 연구이다. Atlas device simulation을 이용하여 표면에 형성된 pyramid의 각도는 $54.74^{\circ}$에서 $71.56^{\circ}$ 가변하였으며 pyramid height은 5에서 $20{\mu}m$ 크기로 가변하여 반사도와 흡수율 변화와 상관관계를 분석하였다. 특히 표면 반사도 감소와 실리콘 기판의 흡수율 증가에 가장 큰 영향을 미치는 표면구조의 인자는 pyramid 각도로 나타났으며, 또한 표면의 pyramid 각도 증가에 따라 표면적도 증가하는 결과를 얻을 수 있었다. 본 연구의 표면 구조의 형상에 따른 반사도와 흡수율 최적화 및 표면적 증가에 대한 결과를 태양전지에 적용할 시 단락전류 향상을 통한 효율 향상을 기대할 수 있을 것이다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.11a
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• pp.343-343
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• 2015

고종횡비의 실리콘 관통전극(TSV)은 반도체 3차원 적층을 실현하기 위한 핵심적인 기술이다. TSV의 충전은 주로 전해도금을 이용하는데 무결함 충전을 위해서 도금액에 몇 가지 첨가제(억제제, 가속제, 평탄제)가 포함된다. 본 연구에서는 첨가제 유무 따른 비아 충전 양상 및 무결함 충전에 대한 연구를 진행하였다. 비아 충전 공정을 위해서 직경 10 um, 깊이 50 um의 TSV가 패터닝된 웨이퍼를 준비하였으며 도금 후 단면을 관찰하여 도금의 양상을 비교하였다. 도금액에 첨가제가 포함되지 않는 조건, 억제제와 가속제만 포함된 조건, 세 가지 첨가제가 모두 포함된 조건으로 비아 충전을 실행하였으며 최종적으로 무결함 충전이 되는 첨가제 조건을 찾을 수 있었다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.141-141
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• 2012

고종횡비 10:1 비아를 Si wafer 상에 형성하기 위해 $7{\mu}m$ 직경의 마스크로 포토작업하여 Cr층을 100nm 스퍼터링하여 PR(photo resistor) 대신의 에칭 barrier 막으로 사용하였다. 얼라인, 노광, 현상을 거쳐 Cr에칭, PR 제거후 ICP(inductively coupled plasma) 공정으로 Si deep etching하여 via 직경 $10.16{\mu}m$, 깊이 $102.5{\mu}m$의 고종횡비 비아를 형성하였다. 구리필링도금을 위해서 필수적인 seed layer는 단층 또는 다층의 금속막을 스퍼터링 법으로 형성하였다. 형성된 seed layer 단면을 FE-SEM(Field emission scanning electron microscope)으로 관찰하여 내부에 seed 층의 형성 유무를 확인하였다.

• Transactions on Electrical and Electronic Materials
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• v.6 no.3
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• pp.87-90
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• 2005

$SiO_2$ via-hole etching with a high aspect ratio is a key process in fabricating ULSI devices; however, accumulated charge during plasma etching can cause etching stop, micro-loading effects, and charge build-up damage. To alleviate this concern, charge-up damage sensor was fabricated for the ultimate goal of real-time monitoring of accumulated charge. As an effort to reach the ultimate goal, fabricated sensor was used for electrical potential measurements of via holes between two poly-Si electrodes and roughly characterized under various plasma conditions using statistical design of experiment (DOE). The successful identification of potential difference under various plasma conditions not only supports the evidence of potential charge-up damage, but also leads the direction of future study.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.187-190
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• 2005

High aspect ratio via-hole etching process has emerged as one of the most crucial means to increase component density for ULSI devices. Because of charge accumulation in via-hole, this sophisticated and important process still hold several problems, such as etching stop and loading effects during fabrication of integrated circuits. Indeed, the concern actually depends on accumulated charge. For monitoring accumulated charge during plasma etching process, charge-up monitoring sensor was fabricated and tested under some plasma conditions. This paper presents a neural network-based technique for analyzing and modeling several electrical performance of plasma charge-up monitoring sensor.

• Nuclear Engineering and Technology
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• v.52 no.11
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• pp.2499-2510
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• 2020

We performed 3-D (3-dimensional) IVR (In-Vessel Retention) natural convection experiments simulating the oxide layer in the three-layer configuration, varying the aspect ratio (H/R). Mass transfer experiment was conducted based on the analogy to achieve high Ra_H's of 1.99 × 10¹²-6.90 × 10¹³ with compact facilities. Comparisons with 2-D (2-dimensional) experiments revealed different local heat transfer characteristics on upper and lower boundaries of the oxide layer depending on the H/R. For the 3-D shallow oxide layer, the multi-cell flow patterns appeared and the number of cells was considerably increased with the H/R decreases, which differs with the 2-D experiments that the number of cells was independent on H/R. Thus, the enhancement of the downward heat transfer and the mitigation of the focusing effect were more noticeable in the 3-D experiments.

• Transactions of Materials Processing
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• v.11 no.7
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• pp.608-613
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• 2002

An ultrasonic machining process is efficient and economical means for precision machining of glass and ceramic materials. However, the mechanism of the process with respect to the crack initiation and propagation and the stress development in the ceramic workpiece subsurface arc still not well understood. In this research, we have investigated the basic mechanism of ultrasonic machining of ultrasonic machining of glass by the experimental approach. For this purpose, we designed and fabricated the desktop micro ultrasonic machine. The feed is controlled precisely by using the constant load control system. During machining experiments, the effects of abrasive characteristics and machining conditions on the surface roughness and the material removal rate are measured and compared.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2009.05a
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• pp.44-47
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• 2009

In this paper, limitation of rigid-plastic finite element method caused from rigid-plasticity assumption and numerical problem is investigated in detail and a useful scheme is proposed to get rid of the plastic deformation in rigid or elastic region. A typical example of a possible long bar extrusion process is given, which may be impossible to simulate without using the proposed scheme. The scheme is successfully applied to simulating the long bolt forging processes.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.68-69
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• 2013

금속 씨드 층(seed layer)을 직경 $10{\mu}m$, 깊이 $100{\mu}m$, 고종횡비 10:1 비아에 스퍼터링하였다. 금속 씨드 층의 두께는 스퍼터링 시간, 압력, 및 타겟파워를 변화하여 조절하였다. 금속 씨드층 스퍼터링 후 전기도금에 의해 구리 충전을 시도하였다. 비아의 고종횡비가 증가하면 비아 폭이 좁아져 비아의 하부층과 하단 측면 두께는 비아 상부 측면 두께만큼 충분하지 않아 문제가 될 수 있다. 스퍼터링 조건을 최적화 함으로써 씨드층의 특성을 높이고, 비아 홀 지름의 감소 속도를 줄일 수 있었다. 종래의 스퍼터링 방식을 이용하여 비아 입구의 opening percentage를 약 64%로 하고, 하부 씨드층 두께가 46.7 nm 인 금속 씨드층을 형성할 수 있었다. 이 씨드층 상에 전기도금으로 Cu filling을 성공적으로 할 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.142-144
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• 2009

We demonstrated narrow and good aspect-ratio inkjet-printed silver lines with multi-time over-printing methods. By using this strategy, narrow silver lines were obtained with 200 nm thickness and their width and gap between printed lines of uniform narrow silver lines were 30 ${\mu}m$ and 17 ${\mu}m$, respectively. It also had good conductivity, sheet resistacne of 0.36 ${\Omega}/{\square}$ and specific resistance of $8{\mu}{\Omega}{\cdot}cm$. In current stress test, narrow silver line with 30 ${\mu}m$ width was able to a current flow up to 50 mA (2.1A/$cm^2$). Using surface treatment on poly-arylate substrate with $UVO_3$, we obtained clean-edge narrow line without any edge waviness.