• Transactions of Materials Processing
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• v.6 no.2
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• pp.95-101
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• 1997

The thermal fatigue and wear properties of high speed steel roll which was recently developed were investigated by observing microstructure, by measuring mechanical and physical properties, by conducting thermal fatigue testing, and by measuring the amount of wear in actual mill. High speed steel roll had better thermal fatigue testing, and by measuring the amount of wear in actual mill. High speed steel roll had better thermal fatigue life than high chromium iron roll, which was due to lower carbide content, higher strength, and higher thermal conductivity. The amount of wear of high speed steel roll was nearly the same as that of high chromium iron roll in the first finishing stand, which was due to the oxide formation on the roll surface. However, in the third finishing stand, the wear resistance of high speed steel roll was 2~3 times as good as that of high chromium iron roll because the former had higher hardness at high temperature.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.537-539
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• 2007

Telemetry processing system requires minimum bit transition level in data streams to maintain a bit synchronization while receiving telemetry signal. PN code has a capability of providing the bit transition and is widely used in the packet communication of CCSDS. CCSDS PN code that generator polynomial is $h(x)=x^{8}+x^{7}+x^{5}+x^{3}+1$, and the random bit sequence that is generated from this polynomial is repeated with the cycle of 255 bits. As the resolution of satellite image increases, the size and transmission rate of data increases. To process of huge and bulky size of satellite image, the speed of CCSDS PN Processing is very important. This paper introduces the way of improving the CCSDS PN Processing speed through processing 128 bits at one time using the feature of cyclic structure that repeats after first 255 bytes by grouping the random bit sequence with 1 byte and Intel Streaming SIMD Extensions 2. And this paper includes the comparison data of processing speed between SSE2-applied implementation and not-applied implementation, in addition, the measured value of speed improvement.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.526-529
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• 2007

Due to its inherent feature of high-resolution satellite, there is strong need in some specific area to minimize the processing time required to get a standard image on hand from downlink signal acquisition. However, in general image processing system, it takes considerable time to get image data up to certain level from raw data acquisition because the huge amount of data is dealt sequentially as input data. This paper introduces the high-speed image processing system which generates the image data only for the area selected by user. To achieve the high speed performance, this system includes Quick Look Image display function with sampling, ROI selection function, Image Line Index function, and Distributed processing function. The developed RPS was applied to KOMPSAT-2 320Mbps downlink channel and its effectiveness was successfully demonstrated. This feature to provide the image product very quickly is expected to promote the application of high resolution satellite image.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.341-352
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• 2012

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

• Korean Chemical Engineering Research
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• v.56 no.3
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• pp.343-348
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• 2018

Each of the two polycarbonates (PC) of different molecular weights was blended with acrylonitrile-butadiene-styrene (ABS) under high-shear rate processing to afford PC/ABS. Sizes of ABS dispersed phases and mechanical properties of PC/ABS blends were investigated and high-shear rate processing of PC/ABS was carried out by changing screw speed and processing time. Prepared specimens were examined by scanning electron microscope (SEM) to observe morphology changes. Sizes of ABS dispersed phases in PC/ABS blends were observed to decrease gradually as screw speeds increased. Tensile strengths and elongations of specimens were investigated by universal testing method (UTM) to study the influence of molecular weight of PC exerting on PC/ABS blends. As a result, PC1/ABS blends (PC1: higher molecular weight PC) exhibited more strengthened properties than PC2/ABS (PC2: lower molecular weight PC). The tensile strength of PC1/ABS showed an increasing tendency when the screw speed increased, and the elongation did not show a significant decrease, but increased slightly with increasing shear time at a constant screw speed of 1000 rpm.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.835-836
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• 2006

For non-contact structure vibration displacement measurement system, an algorithm for image processing using high speed CCD camera is introduced. The system sets the target to the structure, take picture using camera and image processing is performed to display the vibration data. The algorithm flow is basic preprocessing, projection data generation and curve fitting to find three crossing points for calibration or one center point in limited area.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.10-16
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• 1994

In case of off-line character recognition with statistical method, the character recognition speed for Korean or Chinese characters is slow since the amount of calculation is huge. To improve this problem, we seperate the recognition steps into several functional stages and implement them with hardwares for each stage so that all the stages can be processed with pipline structure. In accordance with temporal parallel processing, a high speed character recognition system can be implemented. In this paper, we implement a classification hardware, which is one of the several functional stages, to improve the speed by parallel structure with multiple DSPs(Digital Signal Processors). Also, it is designed to be able to expand DSP boards in parallel to make processing faster as much as we wish. We implement the hardware as an add-on board in IBM-PC, and the result of experiment is that it can process about 47-times and 71-times faster with 2 DSPs and 3 DSPs respectively than the IBM-PC(486D$\times$2-66MHz). The effectiveness is proved by developing a high speed OCR(Optical Character Recognizer).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• Journal of the Korean Society for Heat Treatment
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• v.6 no.1
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• pp.1-8
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• 1993

In this paper, the surface roughness influenced by Sm45C hardness in high frequency induction hardening and mechanical characteristics for the changed Hv 598 part and the unchanged hardness Hv 223 part by use of cermet and ceramic cutting tools was experimentally examined. Finally, we could be had some important results by processing surface roughness on cutting conditions such as cutting speed, feed rate, depth of cut and changes of tool nose radius. The results are summarized as follows. 1. In case of the same cutting condition, the hardness of workpiece was high and acquired the best processing surface roughness when the radius of the tool nose had 0.8 mm and feed rate was 0.04 mm/rev. 2. In case of the hardness of workpiece, though the cutting speed didn't have an effect on processing surface roughness, the less feed rate and the more processing surface roughness improved. On the other hand, the low inside the hardness of workpiece, the more cutting speed and the more feed rate increase, the processing surface of roughness improved. 3. Regardless of the hardness of workpiece, the change of the cutting depth didn't have great effect on the surface roughness. 4. On cutting the high surface hardness part with cutting tools of cermet and ceramic, it can be acquired the higher processing surface roughness because it hadn't been taken effect on cutting speed, In case of the cutting process of the low inside hardness part the two cutting tools have acquired the similar processing surface roughness.

• The Journal of Information Technology
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• v.4 no.3
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• pp.155-163
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• 2001

In this paper, we implemented sigmoid active function which make it difficult to design of the digital neuron networks. Therefore, we designed of the high speed processing of the sigmoid function in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. we designed of MAC operation unit and sigmoid processing unit are proved that it could run of the high speed. On the simulation, the faster than 4.6ns on the each order, we expected that it adapted to the implementation of the high speed digital neural network.