• 농업과학연구
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• 제48권3호
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• pp.535-544
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• 2021

When baking, the proper blending or mixing of materials will affect the quality of the product. The mixing strength is important when establishing the optimal conditions for batter, and control of the mixing condition is accordingly an important factor. This study investigated the effects of the mixing speed and time on the quality characteristics of a gluten-free type of rice batter. The batter samples manufactured for this purpose are as follows: control (+) (wheat flour), control (-) (rice flour), T1 (1,800 rpm, 1 min), T2 (1,800 rpm, 2 min), T3 (1,800 rpm, 3 min), T4 (3,600 rpm, 1 min), T5 (3,600 rpm, 2 min), T6 (3,600 rpm, 3 min). In this study, rice flour was used in the T1 to T6 samples. The pH of the batter tended to be higher when the mixing speed was slower and the time was shorter depending on the ultra-high mixing conditions. The moisture content of T3 was highest, and there was no difference according to the ultra-high speed conditions. The specific volumes of the ultra-high mixing treatments were higher than those of the control samples. The relationship between the specific volume, hardness and springiness of rice bread according to the mixing speed and time was weak. Therefore, it is considered that the application of ultra-high speeds when manufacturing gluten-free batter can have a positive effect on improving the production efficiency by reducing the processing time.

• Journal of Information Processing Systems
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• 제16권5호
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• pp.1064-1073
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• 2020

The general situation of system composition and safety management of high-speed railway terminal is investigated and a comprehensive evaluation index system of operational security is established on the basis of railway laws and regulations and previous research results to evaluate the operational security management of the high-speed railway terminal objectively and scientifically. Index weight is determined by introducing interval eigenvalue method (IEM), which aims to reduce the dependence of judgment matrix on consistency test and improve judgment accuracy. Operational security status of a high-speed railway terminal in northwest China is analyzed using the traditional model of fuzzy comprehensive evaluation, and a general technique idea and references for the operational security evaluation of the high-speed railway terminal are provided. IEM is introduced to determine the weight of each index, overcomes shortcomings of traditional analytic hierarchy process (AHP) method, and improves the accuracy and scientificity of the comprehensive evaluation. Risk factors, such as terrorist attacks, bad weather, and building fires, are intentionally avoided in the selection of evaluation indicators due to the complexity of risk factors in the operation of high-speed railway passenger stations and limitation of the length of the paper. However, such risk factors should be considered in the follow-up studies.

• 한국전자파학회논문지
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• 제25권2호
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• pp.251-254
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• 2014

본 논문에서는 주파수 도약 신호를 고속 병렬처리 구조로 설계하여 추출하는 기법에 대해 연구하였다. 주파수 도약 시스템은 반송파 주파수를 무작위한 것으로 보이는 패턴으로 변형시키기 때문에 고정 신호와는 달리 신호를 탐지하기 어렵고, 분석에 많은 시간이 소요되는 특성을 가진다. 이를 해결하기 위해 주파수 도약 신호를 분석하는 방법을 고속병렬처리 기법을 적용하여 설계하였다. 병렬처리를 위해 GPU를 사용하는 CUDA를 사용하였고, 단일처리 사용 결과와의 성능 평가 결과를 비교하였다. 그 결과, 단일처리 대비 연산 수행 속도 면에서 약 8.53배 성능이 향상됨을 확인하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 춘계학술대회 논문집
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• pp.485-486
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• 2009

• 제어로봇시스템학회논문지
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• 제10권2호
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• 한국정보처리학회논문지
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• 제1권1호
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• pp.99-104
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• 1994

본 논문은 LSI의 물리적 레이아웃 설계시 다량의 패턴 데이타를 고속으로 처리할 수 있는 새로운 2차원 병렬처리 방법을 제안한고 메모리와 프로세서간에 데이타를 양방향으로 고속 전송 하는 스위칭 네트워크를 설계하였다.이스위칭 네트워크를 VHDL 설계 시스템을 이용하여 시뮬레이션하여 그 동작을 확인하였다.

• 전자공학회논문지A
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• 제30A권3호
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1999년도 추계학술대회 논문집 - 한국공작기계학회
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• pp.221-226
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• 1999

It can be acquired the high effective productivity through of high speed, precision of machine tools, and then, machine tools will be got a competitive power. Industrially advanced countries already developed that the high speed feed is 50m/min using the high speed ball screw. Also, a lot of problems have happened the feed and servo drive system. It is necessary to study about the character of positioning accuracy, heat generation and high speed/accuracy control for feed/servo drive system of high speed/accuracy. In this study, we make use of high performance vertical machine center with a ball screw of large-scale-lead. Also, we'll apply the high-speed/accuracy control technology in this part of feedforward control, multi-buffering block size, etc. Using the design of the mechanical element and high-speed precision control, the basic design concept can be established.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.26-31
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• 2002

본 연구는 초고속 지능형 라인센터 개발에 관한 것으로서 1 차 년도 볼 스크류 방식의 시험모델에 대한 종합 검토 결과를 바탕으로 2 차 연도에는 리니어 모터를 채택한 라인센터의 시제품 설계에 있어서 고속화를 위한 방안을 모색하고 컴팩트한 경량의 구조를 지향하는 라인 센터 구조물을 설계하였고, 3 차 년도에는 라인센터의 제작 및 종합적인 시험 평가를 통하여 상품화 모델을 정립하고자 하였다.

• 한국컴퓨터정보학회논문지
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• 제10권3호
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• pp.183-188
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• 2005

블록암호알고리즘의 기본 구조인 Feistel 구조는 순차처리 구조이므로 병렬처리가 곤란하다. 그러므로 본 논문은 이러한 순차처리 구조를 변형하여 Feistel 구조가 병렬처리가 가능하도록 하였다. 이를 이용하여 본 논문은 병렬 Feistel 구조를 가지는 DES를 설계하였다. 제안된 병렬 Feistel 구조는 자체의 구조적 문제 때문에 pipeline 방식을 사용할 수 없어 데이터 처리속도와 데이터 보안사이에서 trade-off관계를 가질 수밖에 없었던 DES등과 같은 블록암호알고리즘의 성능을 크게 향상 시킬 수 있었다. 그러므로 Feistel 구조를 적용한 SEED, AES의 Rijndael, Twofish 등에 제안된 방식을 적용할 경우 지금보다 더욱 우월한 보안 기능 및 고속의 처리능력을 발휘하게 될 것이다.