• Progress in Medical Physics
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• v.18 no.1
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• pp.35-41
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• 2007

In this work practical considerations of a pulsed arterial spin labeling MRI are presented to reliable multi-slice perfusion measurements In the human brain. Three parameters were considered in this study. First, In order to improve slice profile and Inversion efficiency of a labeling pulse a high power Inversion pulse of adiabatic hyperbolic secant was designed. A $900^{\circ}$ rotation of the flip angle was provided to make a good slice profile and excellent Inversion efficiency. Second, to minimize contributions of a residual magnetization be4ween Interleaved scans of control and labeling we tested three different conditions which were applied 1) only saturation pulses, 2) only spotter gradients, and 3) combinations of saturation pulses and spotter gradients Applications of bo4h saturation pulses and spoiler gradients minimized the residual magnetization. Finally, to find a minimum gap between a tagged plane and an imaging plane we tested signal changes of the subtracted image between control and labeled Images with varying the gap. The optimum gap was about 20mm. In conclusion, In order to obtain high quality of perfusion Images In human brain It Is Important to use optimum parameters. Before routinely using In clinical studios, we recommend to make optimizations of sequence parameters.

• Journal of Korean Society for Geospatial Information Science
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• v.7 no.2 s.14
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• pp.123-132
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• 1999

With the rapid increases of the amount of data and computing, the parallelization of the computing algorithm becomes necessary more than ever. However the parallelization had been conducted mostly in a super-computer until the rod 1990s, it was not for the general users due to the high price, the complexity of usage, and etc. A new concept for the parallel processing has been emerged in the form of K-clustering form the late 1990s, it becomes an excellent alternative for the applications need high computer power with a relative low cost although the installation and the usage are still difficult to the general users. The mapping algorithms (cut, join, resizing, warping, conversion from raster to vector and vice versa, etc) in GIS are well suited for the parallelization due to the characteristics of the data structure. If those algorithms are manipulated using PC-clustering, the result will be satisfiable in terms of cost and performance since they are processed in real flu with a low cos4 In this paper the tools and the libraries for the parallel processing and PC-clustering we introduced and how those tools and libraries are applied to mapping algorithms in GIS are showed. Parallel programs are developed for the mapping algorithms and the result of the experiments shows that the performance in most algorithms increases almost linearly according to the number of node.

• Journal of IKEEE
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• v.17 no.3
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• pp.378-384
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• 2013

We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of Digital Contents Society
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• v.17 no.1
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• pp.51-57
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• 2016

Distributed Computing attempts to harness a massive computing power using a great numbers of idle PCs resource distributed linked to the internet and processes a variety of applications parallel way such as bio, climate, cryptology, and astronomy. In this paper, we develop internet-distributed computing environment, so that we can analyze High Resolution Rainfall Prediction application in meteorological field. For analyze the rainfall forecast in Korea peninsula, we used QPM(Quantitative Precipitation Model) that is a mesoscale forecasting model. It needs to a lot of time to construct model which consisted of 27KM grid spacing, also the efficiency is degraded. On the other hand, based on this model it is easy to understand the distribution of rainfall calculated in accordance with the detailed topography of the area represented by a small terrain model reflecting the effects 3km radius of detail and terrain can improve the computational efficiency. The model is broken down into detailed area greater the required parallelism and increases the number of compute nodes that efficiency is increased linearly.. This model is distributed divided in two sub-grid distributed units of work to be done in the domain of $20{\times}20$ is networked computing resources.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.49-53
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• 2007

The direct methanol fuel cell (DMFC) is a promising power source for portable applications due to many advantages such as simple construction, compact design, high energy density, and relatively high energy-conversion efficiency. In this work, an electrochemical methanol sensor for monitoring the methanol concentration in direct methanol fuel cells was fabricated using a thin composite nafion membrane as the electrolyte. We have analyzed the I-V characteristic of the fabricated methanol sensor as a function of methanol concentration, catalyst electrode and platinum(Pt) thickness. The fabricated sensor was analyzed by I-V measurement with various methanol concentration. When we measured the sensor characteristics with 10nm Pt and at 1V, the current value was $1.30{\times}10^{-6}A,\;1.96{\times}10^{-6}A\;and\;2.80{\times}10^{-6} A$ for three methanol concentration of 1M, 2M and 3M, respectively. When the methanol concentration was fixed at 2M, the current value of the fabricated device with Pt layers of 5, 10 and 15 nm thickness was $3.06{\times}10^{-6}A,\;1.96{\times}10^{-6}A\;and\;1.00{\times}10^{-6}A$, respectively. These results lead us to the conclusion that when the methanol concentration increases, the output current increases and when the catalyst electrode become thinner, the current increase more. It showed that, the thinner the catalyst electrode, the more electrochemistry become activation.

• Solar Energy
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• v.17 no.4
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• pp.3-11
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• 1997

Because grain boundaries in polycrystalline silicon act as potential barriers and recombination centers for the photo-generated charge carriers, these defects degrade conversion effiency of solar cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatment, various grid pattern, selective wet etching for grain boundaries, buried contact metallization along grain boundaries, grid on metallic thin film. Pretreatment above $900^{\circ}C$ in $N_2$ atmosphere, gettering by $POCl_3$ and Al treatment for back surface field contributed to obtain a high quality poly-Si. To prevent carrier losses at the grain boundaries, we carried out surface treatment using Schimmel etchant. This etchant delineated grain boundaries of $10{\mu}m$ depth as well as surface texturing effect. A metal AI diffusion into grain boundaries on rear side reduced back surface recombination effects at grain boundaries. A combination of fine grid with finger spacing of 0.4mm and buried electrode along grain boundaries improved short circuit current density of solar cell. A ultra-thin Chromium layer of 20nm with transmittance of 80% reduced series resistance. This paper focused on the grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.6
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• pp.66-73
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• 2002

This paper presents ZVZCS(Zero-Voltage and Zero-Current Switching) Three Level DC/DC Converter without primary freewheeling diodes. The new converter presented in this paper used a phase shirt control with a flying capacitor in the primary side to achieve ZVS for the outer switches. A secondary anxiliary circuit which consists of one small capacitor, two small diodes and one coupled inductor, is added in the secondary to provide ZVZCS conditions to primary switches, ZVS for outer switches and ZCS for inner switches. Many advantages include simple secondary auxiliary circuit topology, high efficiency, and low cost make the new converter attractive for high power applications. Also the circulating current flows through the circuit so that it causes the needless coduction loss to be occurred in the devices and the transformer of the circuit The new converter has no primary auxiliary diodes for freewheeling current. The principle of operation, feature and design considerations are illustrated and verified through the experiment with a 1[㎾］ 50[KHz］IGBT based experimental circuit.

• Polymer(Korea)
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• v.37 no.6
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• pp.694-701
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• 2013

A new copolymer named T-TI24T (poly((5,5-(2-butyl-5,6-bisdecyloxy-4,7-di-thiophen-2-yl-isoindole-1,3-dione))- alt-(2,5-thiophene))) based on phthalimide derivative and thiophene is synthesized by the Stille-coupling reaction. The polymer shows relatively high number average molecular weight of 86500 g/mol with good solubility in common organic solvents such as chloroform, 1,2-dichlorobenzene, and toluene and is thermally stable up to $380^{\circ}C$. Besides, it possesses a relatively low highest occupied molecular orbital (HOMO) energy level of -5.33 eV, promising the high open circuit voltage ($V_{oc}$) for photovoltaic applications. Active layer solution of polymer T-TI24T-as a donor and (6)-1-(3-(methoxycarbonyl)- {5}-1-phenyl[5,6]-fullerene (PCBM)-as an acceptor in different weight ratios is applied to fabricate the polymer solar cell devices. The ratio of polymer/PCBM affects the solar cell efficiency and the best performance exhibits in the device with polymer/PCBM = 1:3 (w/w), which shows a power conversion efficiency (PCE) of 0.199% and a $V_{oc}$ of 0.99 V, respectively. Even though the device shows the very low PCE, the $V_{oc}$ is higher than that of well known bulk heterojunction type solar cell based on P3HT:PC61BM (c.a. 0.5 V).

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.121-121
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• 2010

ZnO is a promising material for the application of high efficiency light emitting diodes with short wavelength region for its large bandgap energy of 3.37 eV which is similar to GaN (3.39 eV) at room temperature. The large exciton binding energy of 60 meV in ZnO provide provides higher efficiency of emission for optoelectronic device applications. Several ZnO/ZnMgO multiple quantum well (MQW) structures have been grown on various substrates such as sapphire, GaN, Si, and so on. However, the achievement of high quality ZnO/ZnMgO MQW structures has been somehow limited by the use of lattice-mismatched substrates. Therefore, we propose the optical properties of ZnO/ZnMgO multiple quantum well (MQW) structures with different well widths grown on lattice-matched ZnO substrates by molecular beam epitaxy. Photoluminescence (PL) spectra show MQW emissions at 3.387 and 3.369 eV for the ZnO/ZnMgO MQW samples with well widths of 2 and 5 nm, respectively, due to the quantum confinement effect. Time-resolved PL results show an efficient photo-generated carrier transfer from the barrier to the MQWs, which leads to an increased intensity ratio of the well to barrier emissions for the ZnO/ZnMgO MQW sample with the wider width. From the power-dependent PL spectra, we observed no PL peak shift of MQW emission in both samples, indicating a negligible built-in electric field effect in the ZnO/$Zn_{0.9}Mg_{0.1}O$ MQWs grown on lattice-matched ZnO substrates.