• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.519-528
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• 2006

This thesis is regarding of fabricating wibro PAM. First of all, we need to set specification based on link budget for wibro communication circumstance in order to develop PAM, then we decided specification concerning of wibro PAM by considering TTAS_Ko_06_0082R1 which is standarded in Korea, and IEEE Std. 802. 16d/e which is international standard. We selected the Doherty structure to increase efficiency, and pre-distorter structure to increase linearity. The fabricated PAM has not only a result of $26.5dB{\pm}1.0dB$ gain characteristics and maximum of -14 dB return loss characteristics in full frequency bands and full output ranges, but also a result of 37 dBc at 4 tone IMD characteristics which is improved result of 843 and a result of 31 dBc spurious characteristics which is improved result of 5 dB at 4.77 MHz offset point in status of having 27 % efficiency in the 26 dBm high power amplifier output signal. We confirmed the suggested structure is better than others by comparing with normal structure, balanced structure and Doherty structure without predistorter.

• Korean Journal of Optics and Photonics
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• v.31 no.5
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• pp.218-222
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• 2020

In this paper, we have experimentally demonstrated a 2-kW-class spectrally-beam-combined laser with high beam quality, using narrow-linewidth ytterbium-doped polarization-maintaining fiber amplifiers. Five fiber amplifiers with different center wavelengths were implemented for the spectrally-beam-combined laser. The center wavelengths of the five amplifiers were 1062, 1063, 1064, 1065, and 1066 nm, respectively. A phase-modulated laser diode was used as a seed source for each amplifier. The seed sources were modulated by filtered pseudorandom-bit-sequence (PRBS) signals 5 GHz in linewidth. The polarization-maintaining large-mode-area fiber with a core size of 30 ㎛ was used as a delivery fiber to mitigate the stimulated Brillouin scattering (SBS) effect. The laser beams from five amplifiers were spectrally combined by a multilayer dielectric diffraction grating. The maximum output power and beam quality M² of the combined laser were measured to be 2.3 kW and 1.74, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.5
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• pp.258-270
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• 2014

In this paper, we investigate channel capacity of two kinds of uplink OFDMA (Orthogonal Frequency Division Multiple Access) schemes, i.e. ZCZ (Zero Correlation Zone) code time-spread OFDMA and sparse SC-FDMA (Single Carrier Frequency Division Mmultiple Access) robust to access timing offset (TO) among multiple users. In order to reflect the practical condition, we consider not only access TO among multiple users but also peak to average power ratio (PAPR) which is one of hot issues of uplink OFDMA. In the case with access TO among multiple users, the amplified signal of users by power control might affect a severe interference to signals of other users. Meanwhile, amplified signal by considering distance between user and base station might be distorted due to the limit of amplifier and thus the performance might degrade. In order to achieve the maximum channel capacity, we investigate the combinations of transmit power so called ASF (adaptive scaling factor) by numerical simulations. We check that the channel capacity of the case with ASF increases compared to the case with considering only distance i.e. ASF=1. From the simulation results, In the case of high signal to noise ratio (SNR), ZCZ code time-spread OFDMA achieves higher channel capacity compared to sparse block SC-FDMA. On the other hand, in the case of low SNR, the sparse block SC-FDMA achieves better performance compared to ZCZ time-spread OFDMA.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.269-281
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• 2014

In this paper, a systematic design of a low phase noise voltage-tuned dielectric resonator oscillator(VTDRO) using loop group delay is proposed. Designed VTDRO is closed-loop type and consists of a cascade connection of a resonator, phase shifter, and amplifier. Firstly, a reference VTDRO is fabricated and its phase noise and electrical frequency tuning range are measured. Both the phase noise and electrical frequency tuning range depend on the loop group delay. Then, a required value of loop group delay for a new VTDRO with a low phase noise can be systematically computed. In addition, its phase noise and electrical frequency tuning range can be theoretically estimated using those obtained from the measurement of the reference VTDRO. When the loop group delay increases, the phase noise decreases and the electrical frequency tuning range also decreases. The former predominantly depends on the resonator structure. Therefore we propose a systematic design procedure of a resonator with high group delay characteristics. The measured loop group delay of the new VTDRO is about 700 nsec. The measured phase noise of the new VTDRO show a state-of-the-art performance of 154.5 dBc/Hz at 100 kHz frequency offset and electrical frequency tuning range of 448 kHz for a voltage change of 0~10V. The oscillation power is about 4.39 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.28-34
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• 2010

In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.371-376
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• 2007

We have investigated the lasing characteristics of the InGaAs quantum dot laser diode (QD-LD) and InGaAs quantum well laser diode (QW-LD) operated at the 980 nm wavelength range. The 980-nm lasers are used as a pumping source for a erbium-doped fiber amplifier (EDFA) and it shows high efficiency in long-haul optical fiber network. We have compared the threshold current density, the characteristic temperature, the optical power and the internal efficiency of QD-LD and QW-LD under a pulsed current condition. The QD-LD shows superior performances to the QW-LD. Further optimization of a LD structure is expected to the superior performances of a QD-LD.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.2
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• pp.58-67
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• 1995

The paper describes the variation of magnetic fields caused by the operation of induction motors. The measuring system consists of the self-integrating magnetic field sensor, amplifier, and active integrator. From the calibration experiments, the frequency bandwidth of the magnetic field measuring system ranges from 20[Hz] to 300[kHz] and sensitivity is 0.234(mV/$\mu\textrm{T}$]. The magnetic fields generated under steady state and starting operations of duction motor are recorded by the proposed measuring system, and the fast Fourier transformation(FFT) of the measured data is performed to analyze the harmonic components. A single pulsed magnetic field is strongly caused by direct starting the induction motor, and its peak value is greater than 5 times as compared with the steady state value. The long transient duration and high intensity originates from the large inductance and dynamic characteristic of the induction motor, During the steady state operation of induction motor, subharmonics of magnetic field components, which depend on the pole number of induction motor, are observed. The lower order power-line harmonics can be inferred from the voltage flicker and current ripple which are derived from the torque fluctuation of induction motor. In the case of the induction motor drived by inverter, the harmonics of magnetic field are much more than those caused by direct starting method and are found generally to increase with decreasing the driving frequency.

• Journal of IKEEE
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• v.25 no.1
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.