• Title/Summary/Keyword: High temperature capacitor

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Incorporation of Graphitic Porous Carbon for Synthesis of Composite Carbon Aerogel with Enhanced Electrochemical Performance

  • Singh, Ashish;Kohli, D.K.;Singh, Rashmi;Bhartiya, Sushmita;Singh, M.K.;Karnal, A.K.
    • Journal of Electrochemical Science and Technology
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    • v.12 no.2
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    • pp.204-211
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    • 2021
  • We report, synthesis of high surface area composite carbon aerogel using additive based polymerization technique by incorporating graphitic porous carbon as additive. This additive was separately prepared using sol-gel polymerization of resorcinol-furfuraldehyde in iso-propyl alcohol medium at much above the routine gelation temperature to yield porous carbon (CA-IPA) having graphitic layered morphology. CA-IPA exhibited a unique combination of meso-pore dominated surface area (~ 700 m2/g) and good conductivity of ~ 300 S/m. The composite carbon aerogel (CCA) was synthesized by traditional aqueous medium based resorcinol-formaldehyde gelation with CA-IPA as additive. The presence of CA-IPA favored enhanced meso-porosity as well as contributed to improvement in bulk conductivity. Based on the surface area characteristics, CCA-8 composition having 8% additive was found to be optimum. It showed specific surface area of ~ 2056 m2/g, mesopore area of 827 m2/g and electrical conductivity of 180 S/m. The electrode formed with CCA-8 showed improved electrochemical behavior, with specific capacitance of 148 F/g & ESR < 1 Ω, making it a better choice as super capacitor for energy storage applications.

Study on LiFePO4 Composite Cathode Materials to Enhance Thermal Stability of Hybrid Capacitor (하이브리드 커패시터의 열안정성 개선을 위한 LiFePO4 복합양극 소재에 관한 연구)

  • Kwon, Tae-Soon;Park, Ji-Hyun;Kang, Seok-Won;Jeong, Rag-Gyo;Han, Sang-Jin
    • Korean Chemical Engineering Research
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    • v.55 no.2
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    • pp.242-246
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    • 2017
  • The application of composite cathode materials including $LiFePO_4$ (lithium iron phosphate) of olivine crystal structure, which has high thermal stability, were investigated as alternatives for hybrid battery-capacitors with a $LiMn_2O_4$ (spinel crystal structure) cathode, which exhibits decreased performance at high temperatures due to Mn-dissolution. However, these composite cathode materials have been shown to have a reduction in capacity by conducting life cycle experiments in which a $LiFePO_4$/activated carbon cell was charged and discharged between 1.0 V and 2.3 V at two temperatures, $25^{\circ}C$ and $60^{\circ}C$, which caused a degradation of the anode due to the lowered voltage in the anode. To avoid the degradation of the anode, composite cathodes of $LiFePO_4/LiMn_2O_4$ (50:50 wt%), $LiFePO_4$/activated carbon (50:50 wt%) and $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ (50:50 wt%) were prepared and the life cycle experiments were conducted on these cells. The composite cathode including $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ of layered crystal structure showed stable voltage behavior. The discharge capacity retention ratio of $LiNi_{1/3}Co_{1/3}Mn_{1/3}O_2$ was about twice as high as that of a $LiFePO_4/LiMn_2O_4$ cell at thermal stability experiment for a duration of 1,000 hours charged at 2.3 V and a temperature of $80^{\circ}C$.

A 14b 150MS/s 140mW $2.0mm^2$ 0.13um CMOS ADC for SDR (Software Defined Radio 시스템을 위한 14비트 150MS/s 140mW $2.0mm^2$ 0.13um CMOS A/D 변환기)

  • Yoo, Pil-Seon;Kim, Cha-Dong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.27-35
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    • 2008
  • This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.