• The Journal of the Convergence on Culture Technology
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• v.1 no.3
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• pp.83-85
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• 2015

It has been increased that communicate each other things such as consumer electronics, mobile equipments and wearable computer with serial communication protocol. The conventional method of SPI and I2C high speed serial communication is widely used with 2 pin of clock and data pin. It has been more important than the speed of data transfer to simplify the hardware structure because the IoT components is reduced the hardware complexity. In this paper, we describe the protocol and implementation of serial data transfer with only one pin. The proposed protocol is suitable for the mobile products that send and receive the small amount of data with low speed and low power consumption.

• Journal of IKEEE
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• v.27 no.4
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• pp.501-511
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• 2023

This paper introduces and analyzes SAE J2716 SENT (Single Edge Nibble Transmission) protocol, a technical standard for serial transmission of digital sensor data in automotive applications. SENT can transmit both high-speed sensor data and low-speed sensor data in one data frame and has a total of 6 transmission modes, including 3 high-speed channel modes and 3 low-speed channel modes. In this paper, a SENT controller that supports all six modes of the SENT protocol was designed in Verilog HDL, implemented in FPGA, and verified with an oscilloscope and PC.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.179-186
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• 2007

KTX control systems mutually control OBCS, ATC, MBU, TECA, MDT, ABU, HVAC, TRAE, PID and FDTR, KTX OBCS as master, and controls other sub-control devices as slave, using various serial lines. In order to analyze physical structure of various serial link lines and mutual data transmission structure, serial line analyzer is used in many ways. To use serial line analyzer, prior and professional technics about High Speed Train and experience of using device are necessary. In spite of difficult situation of space and environment where we work for maintenance of High Speed Train, in presenting basic structure about physical connection method aquired by sub-device serial line data collection and about communication data analysis, I hope that this research will be helpful for the person who work for similar area. Also, I hope that this research will help diagnostic work of High Speed Train, which is necessary for test run of independently developed High Speed Train.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.41-49
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• 2004

In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.125-132
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• 2015

PCI Express is high-speed point-to-point serial protocol, the system is designed by analysing loss and jitter through Eye Diagram. It is necessarily analyzing high speed serial signals when the PCI Express Gen3 which has 8Gbps physical signal speed is designed especially. This paper deals with topology extraction, channel analysis, extraction of s-parameters and system signal integrity simulation within transceiver buffer models through PCI Express Gen3 server connecting switch system design. Optimal parameters of transmitter buffer equalizer are found through solution space simulation of de-emphasis and preshoot parameters to compensate channel loss.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1152-1156
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• 2003

For pneumatic valve system control, we need a serial data transmission system with high speed and reliability for information interchange between main computer and I/O devices. This paper presents a set of design techniques for a data communication system that is mainly used for pneumatic valve system control. For this purpose, we first designed hardware modules for an interface between central control module and local node that handles the operation of solenoid control valves. in addition, we developed a communication protocol for construction of rs-485 based multi-drop network and this protocol is basically designed with a kind of polling technique. Finally we evaluated performance of the developed system. the field test results show that, even under high noise environment, the data transmission of 375kbps rate is possible up to 1,500meter without using repeater. In addition, the system developed in this research is easily to be extended for a communication network because of its modular structure.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.4
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• pp.753-758
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• 2009

Recently the high-end CMOS image sensors are developed, conforming to the SMIA CCP2 specification, which is a high-speed low-power serial interface based on LVDS technology. But this kind of technology trend makes the existing equipments are no longer useful, although their capability is still good enough to handle the recent image sensors if there was no interfacing problem. In this paper, we propose and realize a data protocol conversion system that translates the SMIA CCP2 serial signals into the existing 10-bit parallel signals. The proposed system is composed of a de-serializer and a FPCA chip, and thus can be constructed on a small PCB which enables easy integration between the existing equipments and the new high-end image sensors. Besides, the maximum transfer rate by the SMIA specification is also achieved on the implemented system. So it is expected that the implemented system can be used as a general-purpose protocol converter in a variety of sensor-related application fields.

• Bulletin of the Korean Space Science Society
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• 2004.10b
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• pp.223-226
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• 2004

This paper presents a feasibility study of an advanced IO board design for the next generation of low-earth orbit satellites. Advanced IO board design includes sensor interface, NO, D/A, Digital Module, Serial Module etc, and allows to process increasing data rates between IO board and CPU board. The higher data rate involved in modem IO board additionally introduce issues such as noise, fault tolerance, command and data handling, limited pin count and power consumption problems. The experience in KOMPSAT-l and 2 program with this kind of problems resulted in using SMCS chip set, a high speed serial link technology based on IEEE-1355 (Space Wire Protocol) (ESA-ESTEC 2003, Parkes 1999), as a standard for next generation of satellite IO board design.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.98-105
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• 2008

FlexRay is a high-speed communications protocol with high flexibility and reliability. It was devised by automotive manufacturers and semiconductor vendors and implemented as on vehicle LAN protocol using x-by-wire systems. FlexRay provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for automotive applications. In this paper, we first design the FlexRay communication controller, bus guardian protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay system was synthesized using Samsung $0.35{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 76 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with automobile advance alarm system in vehicle applications. The FlexRay system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.519-523
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• 2003

This paper describes the communication system of sequencing sorter. Generally sequencing sorter is a machine that sorts mails by delivery order. And designed sequencing sorter is composed of 5 physical modules. So, it is necessary to communicate with each module and to control this communication. A computer called Machine Management Computer, controls this. This paper is about the communication system with MMC and module controllers. This is PC-based, asynchronous full-duplex 4-wire serial systems. 3 protocol layers are presented and stop-and-wait flow control is adopted. Because designed sequencing sorter has to be operated high speed about 27,000 letters per hour, we analyzed the network traffic in the worst case. So, we could find that the communication system has to use above 115,200bps speed.