• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Korean Journal of Materials Research
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• v.5 no.6
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• pp.754-762
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• 1995

Strontium titanate(SrTiO$_3$) thin film was prepared on Si substrates by RF magnetron sputtering for a high capacitance density required for the next generation of LSTs. The optimum deposition conditions for SrTiO$_3$thin film were investigated by controlling the deposition parameters. The crystallinity of films and the interface reactions between SrTO$_3$film and Si substrate were characterized by XRD and AES respectively. High quality films were obtained by using the mixed gas of Ar and $O_2$for sputtering. The films were deposited at various bias voltages to obtain the optimum conditions for a high quality file. The best crystallinity was obtained at film thickness of 300nm with the sputtering gas of Ar+20% $O_2$and the bias voltage of 100V. The barrier layer of Pt(100nm)/Ti(50nm) was very effective in avoiding the formation of SiO$_2$layer at the interface between SrTiO$_3$film and Si substrate. The capacitor with Au/SrTiO$_3$/Pt/Ti/SiO$_2$/Si structure was prepared to measure the electric and the dielectric properties. The highest capacitance and the lowest leakage current density were obtained by annealing at $600^{\circ}C$ for 2hrs. The typical specific capacitance was 6.4fF/$\textrm{cm}^2$, the relative dielectric constant was 217, and the leakage current density was about 2.0$\times$10$^{-8}$ A/$\textrm{cm}^2$ at the SrTiO$_3$film with the thickness of 300nm.

• The Journal of Engineering Geology
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• v.31 no.3
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• pp.433-445
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• 2021

Plasma blasting by high voltage arc discharge were performed in laboratory-scale soil samples to investigate the fluid penetration efficiency. A plasma blasting device with a large-capacity capacitor and columnar soil samples with a diameter of 80 cm and a height of 60 cm were prepared. Columnar soil samples consist of seven A-samples mixed with sand and silt by ratio of 7:3 and three B-samples by ratio of 9:1. When fluid was injected into A-sample by pressure without plasma blasting, fluid penetrated into soil only near around the borehole, and penetration area ratio was less than 5%. Fluid was injected by plasma blasting with three different discharge energies of 1 kJ, 4 kJ and 9 kJ. When plasma blasting was performed once in the A-samples, penetration area ratios of the fluid were 16-25%. Penetration area ratios were 30-48% when blastings were executed five times consecutively. The largest penetration area by plasma blasting was 9.6 times larger than that by fluid injection by pressure. This indicates that the higher discharge energy of plasma blasting and the more numbers of blasting are, the larger are fluid penetration areas. When five consecutive plasma blasting were carried out in B-sample, fluid penetration area ratios were 33-59%. Penetration areas into B-samples were 1.1-1.4 times larger than those in A-samples when test conditions were the same, indicating that the higher permeability of soil is, the larger is fluid penetration area. The fluid penetration radius was calculated to figure out fluid penetration volume. When the fluid was injected by pressure, the penetration radius was 9 cm. Whereas, the penetration radius was 27-30 cm when blasting were performed 5 times with energy of 9 kJ. The radius increased up to 333% by plasma blasting. All these results indicate that cleaning agent penetrates further and remediation efficiency of contaminated soil will be improved if plasma blasting technology is applied to in situ cleaning of contaminated soil with low permeability.