• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 추계학술대회 논문집
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• pp.47-51
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• 1997

The high speed machining which can improve the production and quality in machining has been adopted remarkably in dietmold industry. As the speed of machine tool spindle increases, the machinability evaluation and monitoring of high speed machining is necessary. In this study, the machinability of 30, 000rpm class spindle was evaluated by using the developed tool dynamometer and the machining properties of high hardened and toughness materials in high speed were examined. Finally, the in-process monitoring technologies of tool wear were presented through the prediction by the experimental formula and pattern recognition by the neural network.

• 한국철도학회논문집
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• 제5권3호
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• pp.142-147
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• 2002

This paper proposes the Systematic Design Methodology of the Korean High Speed Train. High Speed Train does not operate in isolation and is a part of a rail system which is influenced through input and output effects from the environment and from the neighbouring system. To fullfil its overall desired function, such input and output relationships between the systems must be considered in the system boundary conditions. Therefore, the overall interrelationship of all these effects has to be carefully considered during the design process. Here proposed methodology may provide a guide line and criteria for the systematic problem solving method of that highly complex High Speed Train System.

• 한국콘크리트학회:학술대회논문집
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• 한국콘크리트학회 1998년도 가을 학술발표대회 논문집(III)
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• pp.894-899
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• 1998

To absorb the deformation of live load, thermal gradient, shrinkage and creep in bridge structures and general structures, expansion joint has to be established. Especially expansion joint for high-speed railway bridge has to accomodate the static and dynamic forces and it not only has the durability of itself but also maintain the durability of structure by preventing the leakage of water. The actual used product of expansion joint for high-speed railway bridge is only ones made in France, Germany and Japan. In this study, the development process and test results of developed expansion joint are introduced which has the functional operation and durability enough to apply to high-speed railway bridges, roadway bridges and general structures. The tests consist of fatigue-durability test of 3 million times by high-speed rail load, leakage test and jack-up test for verifying the possibility of exchanging it. The performance of developed expansion joint satisfy the specification of Korea High Speed Rail Construction authority.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2005년도 추계학술대회 논문집
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• pp.462-467
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• 2005

Design standard specifications for structures applied to Seoul-Pusan High Speed Rail construction were established in 1991. Those specifications have been changed and supplemented in the process of above construction, and need to improve in accordance with the new criteria for construction works of Korean government. Also, a settlement of the criteria for prevention against disasters of Seoul-Pusan High Speed Rail is needed, and related specifications have been revised. The design criteria for Seoul-Pusan High Speed Rail are enacted with knowhow which resulted from High Speed Rail construction, and those are enacted for the purpose of establishing criteria for High Speed Rail construction in the inside and outside of Korea.

• 한국정밀공학회지
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• 제28권11호
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• pp.1279-1287
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• 2011

Weather strip is a functional component of a car body and doors for leaking protection, isolating outside noise and vibration reduction. Insert metal inserted to the weather strip plays a key role to keep the shape of the weather strip and increase its strength. Insert metal is mainly produced by a press process, which has low productivity and 40% material loss due to the scraps. To solve the problems, a high-speed rolling process for manufacturing the insert metal of weather strip is being attempted. In this study, the insert metal is manufactured by a high-speed rolling process, and its process variables: reduction, relative velocity of rollers and the number of passes, are optimized by using the FEA and the actual tests. The prototype was manufactured by the optimal process.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2001년도 춘계학술대회 논문집(한국공작기계학회)
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• pp.422-428
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• 2001

The term High Speed Machining has been used for many years to describe end milling with small diameter tools at high rotational speeds, typically 10,000 - 100,000 rpm. The process was applied in the aerospace industry for the machining of light alloys, notably aluminium. In recent year, however, the mold and die industry has begun to use the technology for the production of components, including those manufactured from hardened tool steels. With increasing cutting speed used in modern machining operation, the thermal aspects of cutting become more and more important. It not only directly influences in rate of tool wear, but also will affect machining precision recognized as thermal expansion and the roughness of the surface finish. Hence, one needs to accurately evaluate the rate of cutting heat generation and temperature distributions on the machining surface. To overcome the heat generation, we used to cutting fluid. Cutting fluid play a roles in metal cutting process. Mechanically coupled effectiveness of cutting fluids affect to friction coefficient at tool-work-piece interface and cutting temperature and chip control, surface finish, tool wear and form accuracy. Through this study, we examined the behavior of heat generation in high-speed machining and the cooling performance of various cooling methods.

• 전자공학회논문지B
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• 제31B권6호
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• pp.104-110
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• 1994

We proposed a high speed feature extraction algorithm and developed a feature vector extraction chip for high speed character recognition. It is hard to implement a high speed OCR by software alone with statistical method . Thus, the whole recognition process is divided into functional steps, then pipeline processed so that high speed processing is possible with temporal parallelism of the steps. In this paper we discuss the feature extraction step of the functional steps. To extract feature vector, a character image is normalized to 40$\times$40 pixels. Then, it is divided into 5$\times$5 subregions and 4x4 subregions to construct 41 overlapped subregions(10x10 pixels). It requires to execute more than 500 commands to extract a feature vector of a subregion by software. The proposed algorithm, however, requires only 10 cycles since it can extract a feature vector of a columm of subregion in one cycle with array structure. Thus, it is possible to process 12.000 characters per second with the proposed algorithm. The chip is implemented using EPLD and the effectiveness is proved by developing an OCR using it.

• 전기학회논문지
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• 제68권1호
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• pp.108-121
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• 2019

This paper presents the study results on the design of the correction filter to improve the azimuth error estimation of the high-speed guided missile launched from the warship after the transfer alignment. We theoretically proved that the transfer alignment performance is determined by the accuracy of the marine inertial navigation system and the observability of the attitude error state variable in the transfer alignment filter, and that most of navigation errors in high-speed guided missile are caused by azimuth error. In order to improve the azimuth estimation performance of the correction filter, the multiple adaptive estimation method and the adaptive filters adapting the measurement noise covariance or the process noise covariance are proposed. The azimuth estimation performance of the proposed adaptive filter and the existing Kalman filter are compared and analyzed each other for 8 different transfer alignment accuracy cases. As a result of comparison and analysis, it was confirmed that the adaptive filter adapting the process noise covariance has the best azimuth estimation performance. These results can be applied to the design of correction filters for high-speed guided missile.

• ETRI Journal
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• 제41권3호
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• pp.383-395
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• 2019

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high-speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high-speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan-in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.