• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.2
• /
• pp.291-297
• /
• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.7
• /
• pp.1237-1245
• /
• 2006

This paper presented a hardware implementation of ARIA, which is a Korean standard l28-bit block cryptography algorithm. In this work, ARIA was designed technology-independently for application such as ASIC or core-based designs. ARIA algorithm was fitted in FPGA without additional components of hardware or software. It was confirmed that the rate of resource usage is about 19% in Altera EPXAl0F1020CI and the resulting design operates stably in a clock frequency of 36.35MHz, whose encryption/decryption rate was 310.3Mbps. Consequently, the proposed hardware implementation of ARIA is expected to have a lot of application fields which need high speed process such as electronic commerce, mobile communication, network security and the fields requiring lots of data storing where many users need processing large amount of data simultaneously.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.10 no.4
• /
• pp.81-93
• /
• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.4 s.334
• /
• pp.29-36
• /
• 2005

This paper presents the first hardware design of ARIA that KSA(Korea Standards Association) decided as the block encryption standard at Dec. 2004. The ARIA cryptographic algorithm has an efficient involution SPN (Substitution Permutation Network) and is immune to known attacks. The proposed ARIA design based on 1 cycle/round include a dual port ROM to reduce a size of circuit md a high speed round key generator with barrel rotator. ARIA design proposed is implemented with Xilinx VirtexE-1600 FPGA. Throughput is 437 Mbps using 1,491 slices and 16 RAM blocks. To demonstrate the ARIA system operation, we developed a security system cyphering video data of communication though Internet. ARIA addresses applications with high-throughput like data storage and internet security protocol (IPSec and TLS) as well as IC cards.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.14 no.5
• /
• pp.37-47
• /
• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.15 no.2
• /
• pp.319-326
• /
• 2020

PRNGs(Pseudorandom number generators) are essential for generating encryption keys for to secure online communication. A bitstream generated by the PRNG must be generated at high speed to encrypt the big data effectively in a symmetric key cryptosystem and should ensure the randomness of the level to pass through the several statistical tests. CA(Cellular Automata) based PRNGs are known to be easy to implement in hardware and to have better randomness than LFSR based PRNGs. In this paper, we design PRNGs based on PMLCA(Programable Maximum Length CA) that can generate effective key sequences in symmetric key cryptosystem. The proposed PRNGs generate bit streams through nonlinear control method. First, we design a PRNG based on an (m,n)-cell PMLCA ℙ with a single complement vector that produces linear sequences with the long period and analyze the period and the generating polynomial of ℙ. Next, we design an (m,n)-cell PC-MLCA based PRNG with two complement vectors that have the same period as ℙ and generate nonlinear sequences, and analyze the location of outputting the nonlinear sequence.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.2
• /
• pp.21-34
• /
• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.