• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.1
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• pp.18-27
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• 2002

This paper presents an implementation of digital high-performance speed sensorless control system of an induction motor drives with Direct Torque Control(DTC). The system consists of closed loop stator flux and torque observer, speed and torque estimators, two hysteresis controllers, an optimal switching look-up table, IGBT voltage source inverter, and TMS320C31 DSP controller board. The stator flux observer is based on the combined current and voltage model with stator flux feedback adaptive control for wide speed range. The speed estimator is using the model reference adaptive system(MRAS) with rotor flux linkages for speed turning signal estimation. In order to prove the suggested speed sensorless control algorithm, and to obtain a high-dynamic robust adaptive performance, we have some simulations and actual experiments at low(20rpm) and high(1000rpm) speed areas. The developed speed sensorless system are shown a good speed control response characteristic, and high performance features using 2.2[kW] general purposed induction motor.

• Journal of Power Electronics
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• v.10 no.5
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• pp.505-517
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• 2010

In this paper, an intelligent sliding-mode speed controller for achieving favorable decoupling control and high precision speed tracking performance of permanent-magnet synchronous motor (PMSM) drives is proposed. The intelligent controller consists of a sliding-mode controller (SMC) in the speed feed-back loop in addition to an on-line trained wavelet-neural-network controller (WNNC) connected in parallel with the SMC to construct a robust wavelet-neural-network controller (RWNNC). The RWNNC combines the merits of a SMC with the robust characteristics and a WNNC, which combines artificial neural networks for their online learning ability and wavelet decomposition for its identification ability. Theoretical analyses of both SMC and WNNC speed controllers are developed. The WNN is utilized to predict the uncertain system dynamics to relax the requirement of uncertainty bound in the design of a SMC. A computer simulation is developed to demonstrate the effectiveness of the proposed intelligent sliding mode speed controller. An experimental system is established to verify the effectiveness of the proposed control system. All of the control algorithms are implemented on a TMS320C31 DSP-based control computer. The simulated and experimental results confirm that the proposed RWNNC grants robust performance and precise response regardless of load disturbances and PMSM parameter uncertainties.

• The Journal of Korea Robotics Society
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• v.13 no.1
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• pp.72-78
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• 2018

This paper proposes a Dual Controller System for Precision Control (DCSPC) for control of the gripper. The DCSPC consists of two subsystems, CDSP (Controller based DSP) and CARM (Controller based ARM processor). The CDSP is developed on a DSP processor and controls the gripping motor and LVDT. In particular, the CARM is implemented using Linux and ARM processor according to recent research related to open-source. The robot for high-precision assembly is divided into the robot control and the gripper control section and controls CARM and CDSP systems respectively. In this paper, we also proposed and measured the performance of communication API. As a result, it is expected to recognize improvements in communication between CARM and the robot controller, and will continue to conduct relevant research among other commercial robot controllers.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.413-414
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• 2007

Successful speech recognition in noisy environments for intelligent robots depends on the performance of preprocessing elements employed. We propose an architecture that effectively combines adaptive beamforming (ABF) and blind source separation (BSS) algorithms in the spatial domain to avoid permutation ambiguity and heavy computational complexity. We evaluated the structure and assessed its performance with a DSP module. The experimental results of speech recognition test shows that the proposed combined system guarantees high speech recognition rate in the noisy environment and better performance than the ABF and BSS system.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.1
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• pp.129-136
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• 2004

In this paper, we proposed quad variable rates ADPCM coding method for efficient speech transmission and real time porcessing is implemented on TMS320C6711-DSP. The modified ADPCM with four variable coding rates, 16[kbps], 24[kbps], 32[kbps] and 40[kbps] are used for speech window samples for good quality speech transmission at a small data bits and real time encoding and decoding is implemented using DSP. ZCR is used to identify the influence of the noise on the speech signal and to decide the rate change threshold. For noise superior signals, low coding rates are applied to minimize data bit and for noise inferior signals, high coding rates are applied to enhance the speech quality. In most speech telecommunications, silent period takes more than half of the signals, speech quality close to 40[kbps] can be obtained at comparabley low data bits and this is shown by simulation and experiments. TMS320C6711-DSK board has 128K flash memory and performance of 1333MIPS and has meets the requirements for real time implementation of proposed coding algorithm.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.157-159
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• 2014

In this paper, we introduce SlimSRP, an ultra-low-power digital signal processor (DSP) solution for mobile audio and voice applications. So far, application processors (APs) have taken charge of all the tasks in mobile devices. However, they have suffered from short battery life problems to deal with complex usage scenarios, such as always-on voice trigger with continuous audio playback. From extensive analysis of audio and voice application characteristics, SlimSRP is designed to relive the performance and power burden of APs. It employs three-issue VLIW architecture, and the major low-power and high-performance techniques include: (1) an optimized register-file architecture friendly for constants generation, (2) a powerful instruction set to reduce the number of register file accesses and (3) a unique instruction compression scheme that contributes to saved memory size and reduced cache miss. An implementation of SlimSRP runs at up to 200MHz and the logic occupies 95K NAND2 gates in Samsung 28LPP process. The experimental results demonstrate that a MP3 decoder application with a 128kbps 44.1kHz input can run at 5.1MHz and the logic consumes only 22uW/MHz.

• Journal of Broadcast Engineering
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• v.2 no.2
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• pp.86-93
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• 1997

Fast growth of multimedia applications requires new functions for video data processing. such as obj;cted-based video representation and manipulation. which are not supported by 11PEG-l and 11PEG-2. To support these requirements. 11PEG-4 video coding allows users to manipulate every video object easily by decomposing a scene into several video objects and coding each of them independently. However. the large amount of computations and flexible structure of 11PEG-4 video CODEC make it difficult to be implemented by either the general purpose DSP or a dedicated VLSI. In this paper, we propose a hardware architecture using a hybrid of a high performance programmable DSP and an application specific IC to implement a flexible 11PEG-4 video codec requiring the large amount of computations. The application specific IC has the functions of motion estimation and compensation.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1565-1567
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• 2004

Various defects are found in FPD (Flat Panel Display) manufacturing process. So detecting these defects early and reprocessing them is an important factor that reduces the cost of production. In this paper, the bare glass inspection system for the FPD which is the early process inspection system in the FPD manufacturing process is designed and implemented using the high performance and accuracy CCD line scan camera. For the preprocessing of the high speed line image data, the Image Processing Part (IPP) is designed and implemented using high performance DSP (Digital signal Processor), FIFO (First in First out), FPGA (Field Programmable Gate Array) and the Data Management and System Control part are implemented using ARM (Advanced RISC Machine) processor to control many IPP and cameras and to provide remote users with processed data. For evaluating implemented system, experiment environment which has an area camera for reviewing and moving shelf is made.

• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.13-16
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• 1996

A new instantaneous torque control technique is presented for a high performance control of a permanent magnet synchronous motor. Using the model reference adaptive system technique, the linkage flux of the motor is estimated and the torque is instantaneously controlled by the proposed torque controller combining with a variable structure control and space vector PWM. The proposed torque control provides the advantage of reducing the torque pulsation caused by the flux harmonics. This control strategy is applied to the high torque PM synchronous motor drives for direct drive systems and is implemented by using a software of the DSP TMS320C30. The experiments are carried out for this system and the results well demonstrate the effectiveness of the proposed control.

• The KIPS Transactions:PartA
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• v.12A no.4 s.94
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• pp.305-312
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• 2005

In this paper, we present algorithm-level techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform(FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations on high-level and through low-level simulation. For FFT, our designs dissipated an average of $50\%$ less energy than the design from the Xilinx library and $56\%$ less than the DSP. Our designs showed an EAT factor of 10 times improvement over the embedded processor. These results provide a concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that PFGAs can achieve this performance while still dissipating less energy than the other two types of devices.