• Investigative Magnetic Resonance Imaging
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• v.7 no.1
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• pp.12-21
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• 2003

Purpose : In order to overcome limitations in the existing conventional spectrometer, a new spectrometer with advanced functionalities is designed and implemented. Materials and Methods : We designed a spectrometer using the TMS320C6701 DSP capable of 1 giga floating point operations per second (GFLOPS). The spectrometer can generate continuously varying complicate gradient waveforms by real-time calculation, and select image plane interactively. The designed spectrometer is composed of two parts: one is DSP-based digital control part, and the other is analog part generating gradient and RF waveforms, and performing demodulation of the received RF signal. Each recover board can measure 4 channel FID signals simultaneously for parallel imaging, and provides fast reconstruction using the high speed DSP. Results : The developed spectrometer was installed on a 1.5 Tesla whole body MRI system, and performance was tested by various methods. The accurate phase control required in digital modulation and demodulation was tested, and multi-channel acquisition was examined with phase-array coil imaging. Superior image quality is obtained by the developed spectrometer compared to existing commercial spectrometer especially in the fast spin echo images. Conclusion : Interactive control of the selection planes and real-time generation of gradient waveforms are important functions required for advanced imaging such as spiral scan cardiac imaging. Multi-channel acquisition is also highly demanding for parallel imaging. In this paper a spectrometer having such functionalities is designed and developed using the TMS320C6701 DSP having 1 GFLOPS computational power. Accurate phase control was achieved by the digital modulation and demodulation techniques. Superior image qualities are obtained by the developed spectrometer for various imaging techniques including FSE, GE, and angiography compared to those obtained by the existing commercial spectrometer.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.355-359
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• 2001

This paper presents an implementation of digital control system of speed sensorless for Reluctance Synchronous Motor (RSM) drives with DTC. The control system consists of stator flux observer, rotor position/speed/torque estimator, two hysteresis band controllers, an optimal switching look-up table, IGBT voltage source inverter, and TMS320C31 DSP controller by using fully integrated control software. The stator flux observer is based on the combined voltage and current model with stator flux feedback adaptive control that inputs are current and voltage sensing of motor terminal with estimated rotor angle for wide speed range. The rotor position is estimated by observed stator flux-linkage space vector. The estimated rotor speed is determined by differentiation of the rotor position used only in the current model part of the flux observer for a low speed operating area. It does not require the knowledge of any motor parameters, nor particular care for motor starting, In order to prove the suggested control algorithm, we have a simulation and testing at actual experimental system. The developed sensorless control system is shown a good speed control response characteristic results and high performance features in 50/1000 rpm with 1.0Kw RSM having 2.57 ratio of d/q reluctance.

• Journal of Electrical Engineering and Technology
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• v.2 no.1
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• pp.55-60
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• 2007

This paper proposes a hydraulic pump system that uses a variable speed SR drive and constant capacity pump. For the design of the SRM (Switched Reluctance Motor) and digital controller, base speed and rating torque are determined from the mechanical specifications of the hydraulic pump. In order to minimize the power consumption during the maintaining of preset oil-pressure, the pressure control system changes the maximum oil-pressure band and flow rate according to the motor speed. The DSP control system adjusts the oil-pressure and the speed of the SRM from the pressure sensor signal, due to conservation of power consumption by the hydraulic pump. A 2.2Kw, 12/8 pole SR motor and DSP based digital controller are designed and tested with experimental set-up. The test results indicate that the system has some good features such as high efficiency and rapid response characteristics.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.195-198
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• 2006

The technology of Solar Power conversion System is defined as a solar cell that changes the sol ar energy into the direct electric energy, power conversion and control technology that convert the dc power into ac power The solar cell module, power conversion, and a control part in component parts consisting a solar power conversion system have influence on its performance. The roles of power conversion and a control part supply the direct current generated by solar cell module for a load with high efficiency as conveniently as possible in this study, the power conversion systen that can generate solar power using DSC module was developed and its characteristics was experimented. The characteristics of the DSC power conversion system including MOSFET and DSP micro processor, high speed devices, was simulated using Psim. According to the results, converter and inverter was manufactured in detail and the performance characteristics were studied.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.66-73
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• 2002

As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.151-161
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• 2009

Audio Video Standard (AVS) is the audio and video compression standard that was developed for domestic video applications in China. AVS employs low complexity tools to minimize degradation of RD performance of the state-the-art video codec, H.264/AVC. The AVS video codec consists of $8{\times}8$ block prediction and the same size transform to improve compression efficiency for VGA and higher resolution sequences. Currently, the AVS has been adopted more and more for IPTV services and mobile applications in China. So, many consumer electronics companies and multimedia-related laboratories have been developing applications and chips for the AVS. In this paper, we implemented the AVS video decoder and optimize it on TI's Davinci EVM DSP board. For improving the decoding speed and clocks, we removed unnecessary memory operations and we also used high-speed VLD algorithm, linear assembly, intrinsic functions and so forth. Test results show that decoding speed of the optimized decoder is $5{\sim}7$ times faster than that of the reference software (RM 5.2J).

• Journal of Power Electronics
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• v.3 no.1
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• pp.1-9
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• 2003

This paper presents a performance analysis of typical Auxiliary Resonant Commutation Snubber-assisted three phase voltage source soft switching inverter which can operate under a condition of Zero Voltage Switching (ZVS) using a digital control scheme which is suitable for high power applications compared with resonant DC link snubber assisted soft switching inverter. The system performances of this inverter are illustrated and evaluated on the basis of experimental results.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Journal of Power Electronics
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• v.2 no.4
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• pp.288-296
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• 2002

In this paper, a high frequency transformer - assisted auxiliary active resonant commutated snubber (HFTA-ARCS) for voltage source soft switching pulse width modulated power conversion circuits is presented. A three phase voltage source type soft switching inverter incorporating HFTA-ARCS circuits in its three bridge legs can reduce current rating of auxiliary active power switches and has sensorless simplified control scheme which any specified boost current management is not required for soft switching. Its operation principle and digital control scheme are described and a practical design method of circuit parameters on this HFTA-ARCS circuit is also introduced on the basis of computer simulation. Moreover, this space voltage vector modulated soft switching inverter system with DSP-based digital control scheme Is discussed and its effectiveness is proved on the basis of performance evaluations. The operating performances of this inverter system are also compared with those of conventional three-phase hard switching inverter under practical conditions of specified parameters.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.6
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• pp.538-545
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• 2001

In this paper a gearless drive system using a permanent-maget synchronous motor for high speed elevators is addressed. The application of permanent magnet synchronous motor to an elevator traction machine enables several improvements including higher efficiency better ride comfort smaller size and lighter weight and so on A PWM boost converter has been also adopted so that DC-link voltage regulation bi-directional power flow and controllable power factor with reduced input current harmonics are possible. To increase the reliability and performance of overall control system the unified control board which can include the car and group controller as well as PWN converter/inverter controller has been designed based on a DSP TMS320VV33. In addition the dynamic load simulator system has been developed so that the drive system of high speed elevator can be tested and evaluated without and limitation on ride distance. Some experimental results are given to verify the effectiveness of the developed system.