• IE interfaces
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• v.17 no.1
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• pp.128-141
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• 2004

Although a number of container terminal simulators have been developed for various purposes, none of the existing simulators allow the system structure to reuse the system structure depending on application. Our goal is to develop highly reusable, highly inter-operable and flexible container terminal simulation system. The High Level Architecture(HLA) is an architecture for reuse and inter-operation of simulation. It is based on premise that no simulation can satisfy all use and users. An individual simulation or set of simulations developed for one purpose can be applied to another application under the HLA concept of the federation : a composable set of interacting simulations. The intent of the HLA is a structure which will support reuse of capabilities available in different simulations, ultimately reducing the cost and time required to create a synthetic environment for a new purpose, and the possibility of distributed collaborative development of complex simulation applications. In this paper, we discuss the design of a HLA-based port container terminal simulation system. Furthermore, we describe various technical motivations for HLA, the key elements of the architecture and how they are minimum and essential to the goal of reuse and interoperability.

• Journal of the Korea Society for Simulation
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• v.14 no.3
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• pp.79-90
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• 2005

There are plenty of optimization models for the signal-system of a single intersection and area traffic. Some of those models are adopted for the real traffic signal control system. The simulators for a single crossroad have been developed, so that we could evaluate optimization models and traffic control systems. However, the simulators for the area traffic are still being developed. Therefore, there are many limitations in the analysis and evaluation for area traffic control system. The area traffic is consisted of several intersections which are very complicated and many traffic strategies are adopted for the control system. This paper features an effective area traffic control system based on the High Lever Architecture(HLA). In this paper, we discuss the design of HLA-based area traffic control simulation. We describe technical motivations for the HLA, the key elements of the architecture and how they are minimum and essential to the goal of reuse and interoperability. A distributed simulation with HLA/RTI provides stable and satisfactory experimental results. Moreover, the prototype traffic control system provides reliable accomplishment compared to the NETSIM and TRANSYT-7F models.

• International Journal of High-Rise Buildings
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• v.8 no.1
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• pp.57-69
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• 2019

After decades of high-speed development, designing tall buildings as critical components of urban habitat, rather than simply standing aloof from their environments, has become an important concern in many Asian cities. Nevertheless, the lack of quantitative understanding cannot support efficient architectural design or urban renewal that targets better place-making. This study attempts to fill the gap by providing a typological approach for measuring the social impact of tall buildings' ground conditions: that is, public space, podiums, and interfaces. The central business districts (CBD) of three Asian cities, Shanghai, Hong Kong, and Singapore, were selected as cases. Typical patterns and categories of lower-level public spaces among the three CBDs were abstracted via typological analyses and field study. The following evaluation is achieved through the analytic hierarchy process (AHP). This quantified approach helps to provide a visualization of high or low positive social impacts of tall buildings' lower-level public spaces among the three cases. This study also helps to suggest a design code for tall buildings aimed at a more human-oriented urban habitat.

• ETRI Journal
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• v.33 no.4
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• pp.648-651
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• 2011

This letter presents a highly efficient rack-level DC power architecture combined with a node-level DC uninterruptible power supply (UPS). The proposed system can provide almost the equivalent power efficiency of a high-voltage DC data center without any change in the existing power infrastructure. The node-level DC UPS combined with a power distribution board provides high power efficiency as well as lower UPS installation costs. Implemented on a rack, the entire power system can be monitored through a network.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1585-1590
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• 1991

This paper presents the principles for design of autonomous systems whose behavior is based on models that support the various tasks that must be performed. We propose a model-based architecture aimed at reducing the computational demands required to integrate high level symbolic models with low level dynamic models. Model construction methods are illustrated to outfit such an architecture with the models needed to meet given objectives.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1281-1292
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• 2014

Photovoltaic (PV) solar systems with series-connected module integrated converters (MICs) are receiving increased attention because of their ability to create high output voltage while performing local maximum power point tracking (MPPT) control for individual solar panels, which is a solution for partial shading effects in PV systems at panel level. To eliminate the partial shading effects in PV system more effectively, sub-MICs are utilized at the cell level or grouped cell level within a PV solar panel. This study presents the results of a series-output-connection MPPT (SOC-MPPT) controller for sub-MIC architecture using a single sensor at the output and a single digital MPPT controller (sub-MIC SOC-MPPT controller and architecture). The sub-MIC SOC-MPPT controller and architecture are investigated based on boost type sub-MICs. Experimental results under steady-state and transient conditions are presented to verify the performance of the controller and the effectiveness of the architecture.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.161-164
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• 2000

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

• The Journal of Aerospace Industry
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• s.53
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• pp.57-77
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• 2000

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.10-27
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• 2005

In this paper, we propose a high level design architecture of WCDMA(UMTS) base station modem and synchronization algorithms applied to the proposed architecture. Also analysis of each synchronization algorithm and performance evaluation of fixed point designed modem are shown. Since the target system is base station modem, each synchronization algorithm is designed for its stable operation. To minimize implementation complexity, optimum fixed point design for best operation of synchronization algorithms is performed. We performed symbol level link simulation with fixed point designed modem simulator for data rate of 12.2kbps, 64kbps, 144kbps, and 384kbps. We compared performance results to the minimum requirements specified in 3GPP TS 25.104(Release 5). Extensive computer simulation shows that the proposed modem architecture has stable operation and outperform the minimum requirement by 2 dB. The proposed modem architecture has been applied in the implementation of WCDMA reverse link receiver modem chip successfully.

• Journal of Computing Science and Engineering
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• v.8 no.4
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.