• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 1998년도 The Korea Society for Simulation 98 춘계학술대회 논문집
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• pp.38-42
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• 1998

본 논문에서는 DEVS 형식론과 High Level Architecture에 기반을 둔 이 기종 시뮬레이션 환경의 구축에 대해 기술한다. DEVS 형식론은 여러 가지 방법으로 기술된 모델들을 동일한 형식론으로 간주하기 위해 사용되었다. 즉, 이산사건 모델링을 위한 세가지 세계관(world view)으로 기술된 시뮬레이션 모델들을 DEVS 형식론으로의 변환을 통해 전체적으로는 DEVS 형식론만을 사용한 것과 동일한 형태로 표현되도록 하였다. High Level Architecture는 시뮬레이션 수행시의 상호 연동성을 보장하기 위해 사용되었다. 이때, DEVS 형식론과 High Level Architecture에서의 시뮬레이션 시간 진행 방법이 다르기 때문에 이의 해결을 Synchronizer, EOS 방법을 제안하였다.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.78-85
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• 2008

네트워크 SoC 칩을 대상으로 SystemC를 이용한 High-level 설계 방법을 연구하였다. 실제 Verilog RTL 모델과 비교하여 깊이있는 Architecture 구조탐색과 정확한 SystemC 모델 cycle 검증을 토대로 하여 High-level 설계를 강조할 것이다. 대다수 High-level 설계와 접근방법과 다르게, SystemC 모델과 Verilog RTL 모델의 성능을 비교해 보고, SystemC-based platform을 검증하기 위해 On-chip test board 측정 데이터를 이용하였다. 이 논문에서는 High-level 설계기법이 RTL 모델과 같은 정확성을 얻을 수 있을 뿐만 아니라, RTL 모델보다 100배 이상 빠른 시뮬레이션 속도를 달성할 수 있음을 보여 주었다. 그리고, 아키텍처 구조탐색을 통해서 시스템 성능하락의 원인을 파악하고, 대안을 찾아보았다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1039-1043
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• 2005

Despite the many significant advances made in robot architecture, the basic approaches are deliberative and reactive methods. They are quite different in recognizing outer environment and inner operating mechanism. For this reason, they have almost opposite characteristics. Later, researchers integrate these two approaches into hybrid architecture. In such architecture, Reactive module also called low-level motion control module have advantage in real-time reacting and sensing outer environment; Deliberative module also called high-level task planning module is good at planning task using world knowledge, reasoning and intelligent computing. This paper presents a framework of the integrated planning and control for mobile robot navigation. Unlike the existing hybrid architecture, it learns topological map from the world map by using MST (Minimum Spanning Tree)-based SOFM (Self-Organizing Feature Map) algorithm. High-level planning module plans simple tasks to low-level control module and low-level control module feedbacks the environment information to high-level planning module. This method allows for a tight integration between high-level and low-level modules, which provide real-time performance and strong adaptability and reactivity to outer environment and its unforeseen changes. This proposed framework is verified by simulation.

• 한국CDE학회논문집
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• 제21권3호
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• pp.313-324
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• 2016

As building information modeling (BIM) is expanding its influence in various fields of architecture, engineering, construction and facility management (AEC-FM) industry, BIM-based automated code compliance checking has become possible prospects. For the automated code compliance checking, requirements in building code need to be processed into explicit representation that enables automated reasoning. This paper aims to develop high-level methods that translate verb phrases into explicit representation. The high-level methods represent conditions, properties, and related actions of the building objects and clarify the core content of the constraints. The authors analyze building permit requirements in Korea Building Code and establish a standardized process of deriving the high-level methods. As a result, 60 kinds of the high-level methods were derived. In addition, method classification, analysis, and application are introduced. This study will contribute to the representation of explicit building code sentences and establishment of the automated building permit system of Korea.

• 전자공학회논문지C
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• 제34C권3호
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• pp.1-10
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• 1997

We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.

• 디지털산업정보학회논문지
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• 제11권3호
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• pp.31-43
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• 2015

In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).

• 한국군사과학기술학회지
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• 제11권2호
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• pp.80-87
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• 2008

The LVC(Live, Virtual, Constructive) system of CTC(Combat Training Center) is at the very cutting edge of modeling and simulation technology, which has become widely accepted an enabler for a new military training transformation. In this paper, the architecture of LVC system is proposed for the Korean brigade-level CTC, and high level operational architecture, system architecture, and technical standard architecture are suggested.

• International Journal of Naval Architecture and Ocean Engineering
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• 제4권3호
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• pp.211-227
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• 2012

To implement a combined discrete event and discrete time simulation such as submarine diving simulation in a distributed environment, e.g., in the High Level Architecture (HLA)/Run-Time Infrastructure (RTI), a HLA interface, which can easily connect combined models with the HLA/RTI, was developed in this study. To verify the function and performance of the HLA interface, it was applied to the submarine dive scenario in a distributed environment, and the distributed simulation shows the same results as the stand-alone simulation. Finally, by adding a visualization model to the simulation and by editing this model, we can confirm that the HLA interface can provide user-friendly functions such as adding new model and editing a model.

• 대한교통학회지
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• 제19권6호
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• pp.19-31
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• 2001

우리 나라 환경에 적합한 국가 지능형 교통체계(ITS: Intelligent Transportation Systems)의 구현을 위한 국가 아키텍쳐 수립연구가 국토연구원과 관련 학계와 산업계의 협동연구로 지난 3년간 수행되어 천여 페이지에 달하는 국가 아키텍쳐가 수립된 바 있다. 본 논문에서는 이를 위해서 고안된 도메인 수준과 논리 수준 및 물리 수준의 아키텍쳐 모형과 방법론을 제시한다. 도메인 수준의 아키텍쳐는 ITS를 구현함에 있어 관계되는 영역간의 국가적 협동체계를 이룩하기 위한 국가적 기본 틀이고 논리수준의 아키텍쳐는 서비스의 중복/사각/상충을 방지하기 위한 국가적 기본 틀이며 물리수준의 아키텍쳐는 서비스 시스템을 구축함에 있어 물리적 정보기술 자원을 효율적으로 할당하여 시스템 구축의 경제성과 효율성을 도모하기 위한 시스템의 물리적 구성 틀이다. 이를 위한 모델과 기법은 고전적 컴퓨터 기반 시스템공학에서의 프로세스 지향적 사고와 기법을 수정 보완하고 확장한 것으로 고 수준(High Level)에서의 아키텍쳐 구상에 적절한 것이다. 저 수준(Low Level)의 아키텍쳐는 설계 수준에서 이루어지는 것으로 전제하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.284-299
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• 2014

Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.