• Proceedings of the Korea Society for Simulation Conference
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• 1998.03a
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• pp.38-42
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• 1998

본 논문에서는 DEVS 형식론과 High Level Architecture에 기반을 둔 이 기종 시뮬레이션 환경의 구축에 대해 기술한다. DEVS 형식론은 여러 가지 방법으로 기술된 모델들을 동일한 형식론으로 간주하기 위해 사용되었다. 즉, 이산사건 모델링을 위한 세가지 세계관(world view)으로 기술된 시뮬레이션 모델들을 DEVS 형식론으로의 변환을 통해 전체적으로는 DEVS 형식론만을 사용한 것과 동일한 형태로 표현되도록 하였다. High Level Architecture는 시뮬레이션 수행시의 상호 연동성을 보장하기 위해 사용되었다. 이때, DEVS 형식론과 High Level Architecture에서의 시뮬레이션 시간 진행 방법이 다르기 때문에 이의 해결을 Synchronizer, EOS 방법을 제안하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1039-1043
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• 2005

Despite the many significant advances made in robot architecture, the basic approaches are deliberative and reactive methods. They are quite different in recognizing outer environment and inner operating mechanism. For this reason, they have almost opposite characteristics. Later, researchers integrate these two approaches into hybrid architecture. In such architecture, Reactive module also called low-level motion control module have advantage in real-time reacting and sensing outer environment; Deliberative module also called high-level task planning module is good at planning task using world knowledge, reasoning and intelligent computing. This paper presents a framework of the integrated planning and control for mobile robot navigation. Unlike the existing hybrid architecture, it learns topological map from the world map by using MST (Minimum Spanning Tree)-based SOFM (Self-Organizing Feature Map) algorithm. High-level planning module plans simple tasks to low-level control module and low-level control module feedbacks the environment information to high-level planning module. This method allows for a tight integration between high-level and low-level modules, which provide real-time performance and strong adaptability and reactivity to outer environment and its unforeseen changes. This proposed framework is verified by simulation.

• Korean Journal of Computational Design and Engineering
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• v.21 no.3
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• pp.313-324
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• 2016

As building information modeling (BIM) is expanding its influence in various fields of architecture, engineering, construction and facility management (AEC-FM) industry, BIM-based automated code compliance checking has become possible prospects. For the automated code compliance checking, requirements in building code need to be processed into explicit representation that enables automated reasoning. This paper aims to develop high-level methods that translate verb phrases into explicit representation. The high-level methods represent conditions, properties, and related actions of the building objects and clarify the core content of the constraints. The authors analyze building permit requirements in Korea Building Code and establish a standardized process of deriving the high-level methods. As a result, 60 kinds of the high-level methods were derived. In addition, method classification, analysis, and application are introduced. This study will contribute to the representation of explicit building code sentences and establishment of the automated building permit system of Korea.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.1-10
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• 1997

We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.3
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• pp.31-43
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• 2015

In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).

• Journal of the Korea Institute of Military Science and Technology
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• v.11 no.2
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• pp.80-87
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• 2008

The LVC(Live, Virtual, Constructive) system of CTC(Combat Training Center) is at the very cutting edge of modeling and simulation technology, which has become widely accepted an enabler for a new military training transformation. In this paper, the architecture of LVC system is proposed for the Korean brigade-level CTC, and high level operational architecture, system architecture, and technical standard architecture are suggested.

• International Journal of Naval Architecture and Ocean Engineering
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• v.4 no.3
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• pp.211-227
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• 2012

To implement a combined discrete event and discrete time simulation such as submarine diving simulation in a distributed environment, e.g., in the High Level Architecture (HLA)/Run-Time Infrastructure (RTI), a HLA interface, which can easily connect combined models with the HLA/RTI, was developed in this study. To verify the function and performance of the HLA interface, it was applied to the submarine dive scenario in a distributed environment, and the distributed simulation shows the same results as the stand-alone simulation. Finally, by adding a visualization model to the simulation and by editing this model, we can confirm that the HLA interface can provide user-friendly functions such as adding new model and editing a model.

• Journal of Korean Society of Transportation
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• v.19 no.6
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• pp.19-31
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• 2001

In this paper, 3 layered architecture model and related design guidelines are proposed, which have been actually applied in our national ITS-Architecture design. The domain architecture as the 1st layer is to structure all ITS related domains for maximizing the co-operability in national level. The logical architecture as the 2nd layer is to structure all ITS related application-systems for minimizing duplications, conflicts and dead-zones in service level and maximizing the co-operability in application-system level. The physical architecture as the 3rd layer is to structure all IT(Information Technology) related physical resources for maximizing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.284-299
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• 2014

Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.