• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.403-406
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• 1998

Electroluminescence(EL) come from the light emission obtained by electrical excitation energy passing through a phosphor layer under applied high electrical field. The preparation and characterizations of light emitting ACPEL(alternating-current powder electroluminescent) cell based on two kinds of phosphor mixed ZnS:Mn, Cu and ZnS:Cu phosphor. Basic structure is ITO/Mixed Phosphor/insulator/Al sheet, each layer was mixed by binder, which concentration 11p for phosphor, 8p for insulator. Dielectric properties was investigated first and emission properties of P-LED based on ZnS:Mn,Cu/ZnS:Cu,Br mixture. Emission spectra exhibits two kinds of main peaks at 100V, 1kHz sinusoidal excitation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.467-468
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• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFT) that consist of indium-zinc-oxide (IZO), PVP (poly-vinyl phenol), and Ni for the source-drain (S/D) electrode, gate dielectric, and gate electrode, respectively. The IZO S/D electrodes of which the work function is well matched to that of P3HT were deposited on a P3HT channel by thermal evaporation of IZO and showed a moderately low but still effective transmittance of ~25% in the visible range along with a good sheet resistance of ${\sim}60{\Omega}/{\square}$. The maximum saturation current of our P3HT-based TFT was about $15{\mu}A$ at a gate bias of -40V showing a high field effect mobility of $0.05cm^2/Vs$ in the dark, and the on/off current ratio of our TFT was about $5{\times}10^5$. It is concluded that jointly adopting IZO for the S/D electrode and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• 한국전기전자재료학회논문지
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• 제16권2호
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• pp.151-156
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• 2003

High temperature superconductor can only be applied against an engineering specofication that has to be determined for each particular application form the design requirements for economic viability and for operation margins in service. However, in order to realize the HTS transformer, it is necessary to establish the high voltage insulation technique in cryogenic temperature. Therefore, the composite insulation of double pancake coil type transformer are described and AC breakdown voltage characteristics of liquid nitrogen(LN$_2$) under HTS pancake coil electrode made by Bi-2223/Ag are studied. The Breakdown of LN$_2$ is dominated electrode shape and distance. The influence of pressure on breakdown voltage is discussed with th different electrode. For the electrical insulation design of turn-to-turn insulation for the HTS transformer, we tested breakdown strength of insulation sheet under varying pressure. And we investigated surface flashover properties of LN$_2$ and complex conition of cryogenic gaseous nitrogen(CGN$_2$) obove a LN$_2$ surface. The surface voltage of GFRP was measured as a function of thickness and electrode distance in LN$_2$ and complex condition of CGN$_2$ above a LN$_2$ surface. this research presented information of electrical insulation design for double pancake coil(DPC) type HTS transformer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.3-4
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• 2006

In this paper, a nickel silicide technology with post-silicidation annealing effect for thin film SOI devices is investigated in detail. Although lower resistivity Ni silicide can be easily obtained at low forming temperature, poor thermal stability and changing of characteristic are serious problems during the post silicidation annealing like ILD (Inter Layer Dielectric) deposition or metallization. So these effects are observed as deposited Ni thickness differently on As doped SOI (Si film 30nm). Especially, the sheet resistance of Ni thickness deposited 20nm was lower than 30nm before the post silicidation annealing. But after the post silicidation annealing, the sheet resistance was changed. Therefore, in thin film SOI MOSFETs or Ni-FUSI technology that the Si film is less than 50nm, it is important to decide the thickness of deposited Ni in order to avoid forming high resistivity silicide.

• Journal of Electrical Engineering and Technology
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• 제13권4호
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• pp.1638-1643
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• 2018

Multi-layer ceramic capacitors as decoupling capacitor were fabricated by dielectric composition with a high dielectric constant. The fabricated decoupling capacitors were embedded in the PCB of the 10G RF transceiver module and evaluated for the characteristics of electrical noise by the level of AC input voltage. In order to further improve the electrical properties of the $BaTiO_3$ based composite, glass frit, MgO, $Y_2O_3$, $Mn_3O$, $V_2O_5$, $BaCO_3$, $SiO_2$, and $Al_2O_3$ were used as additives. The electrical properties of the composites were determined by various amounts of additives and optimum sintering temperature. As a result of the optimized composite, it was possible to obtain a density of $5.77g/cm^3$, a dielectric constant of 1994, and an insulation resistance of $2.91{\times}10^{12}{\Omega}$ at an additive content of 5wt% and a sintering temperature of $1250^{\circ}C$. After forming a $2.5{\mu}m$ green sheet using the doctor blade method, a total of 77 layers were laminated and sintered at $1180^{\circ}C$. A decoupling capacitor with a size of $0.6mm(W){\times}0.3mm(L){\times}0.3mm(T)$ (width, length and thickness, respectively) and a capacitance of 100 nF was embedded using a PCB process for the 10G RF Transceiver modules. In the range of AC input voltage 400mmV @ 500kHz to 2200mV @ 900kHz, the embedded 10G RF Transceiver modules evaluated that it has better electrical performance than the non-embedded modules.

• 한국컴퓨터산업학회논문지
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• 제5권2호
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• pp.331-336
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• 2004

본 논문은 GPS/GSM 이중대역으로 차량 내부 장착용 텔레매틱스 안테나를 제안하였다. 고유 전율을 가지는 유전체를 사용하지 않으며 두 안테나를 같은 평면에 1mm의 두께를 가지는 fr4기판 위에 설계를 하였다. 이러한 방법으로 제작비용의 절감과 제작공정의 간소화를 추구하였다 GSM 대역은 평면 역 F형 안테나(PIFA)로 구현하였고 GPS 대역의 안테나를 마이크로스 트립 안테나(MSA)로 설계한 PIFA-MSA를 제안하였다. PIFA-MSA는 포트간 격리도 특성을 고려하여 상용 안테나보다 낮게 구현하면서 두 안테나간 편파를 수직으로 배열하여 격리도 특성을 극대화했으며 설계규격 또한 만족 시켰다.

• 마이크로전자및패키징학회지
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• 제8권3호
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• pp.69-75
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• 2001

후막광식각 기술은 스크린 인쇄 등의 일반적 후막공정에 노광 및 현상등의 리소그라피 공정 을 접목시킨 새로운 기술이다. 그린시트를 적층한 후 감광성 Ag 페이스트를 도포하고, 패턴을 노광, 현상, 동시소성하여 스크린 인쇄법으로는 어려운 25 $\mu\textrm{m}$ 선폭과 25 $\mu\textrm{m}$ 선간공백을 구현하였다. 알루미나 기판을 사용하였을 경우에도 유사한 방법으로 20 $\mu\textrm{m}$에 가까운 선폭이 구현 가능하였으며, 노광량과 현상시간이 미세라인 형성에 있어서 가장 중요한 공정변수임을 확인하였다. 또한, 광식각 기술을 이용하여 정밀도가 높고 고주파 대역에서 전송특성이 우수한 microstrip 전송선로와 series gap 공진기를 제작하여, 이로부터 기판의 유전률 및 유전손실을 계산하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.375-375
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• 2012

Graphene is a sp2-hybridized carbon sheet with an atomic-level thickness and a wide range of graphene applications has been intensely investigated due to its unique electrical, optical, and mechanical properties. In particular, hybrid graphene structures combined with various nanomaterials have been studied in energy- and sensor-based applications due to the high conductivity, large surface area and enhanced reactivity of the nanostructures. Conventional metal-catalytic growth method, however, makes useful applications difficult since a transfer process, used to separate graphene from the metal substrate, should be required. Recently several papers have been published on direct graphene growth on the two dimensional planar substrates, but it is necessary to explore a direct growth of hierarchical nanostructures for the future graphene applications. In this study, uniform graphene layers were successfully synthesized on highly dense dielectric nanowires (NWs) without any external catalysts. We also demonstrated that the graphene morphology on NWs can be controlled by the growth parameters, such as temperature or partial pressure in chemical vapor deposition (CVD) system. This direct growth method can be readily applied to the fabrication of nanoscale graphene electrode with designed structures because a wide range of nanostructured template is available. In addition, we believe that the direct growth growth approach and morphological control of graphene are promising for the advanced graphene applications such as super capacitors or bio-sensors.

• 대한전자공학회논문지SD
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• 제48권3호
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• pp.7-11
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• 2011

본 논문에서는 간단하면서도 수율 높은 유기박막트랜지스터(OTFT)의 소스/드레인 전극 형성을 위한 인쇄공정을 제안하였다. 게이트 유전체인 PVP (poly 4-vinylphenol)에 불소계 화합물을 3000 ppm 첨가하여 표면에너지를 56 $mJ/m^2$에서 45 $mJ/m^2$로 줄이고, 소스/드레인 전극이 형성될 영역은 포토리소그라피로 형상화 한 후 산소 플라즈마로 선택적으로 표면처리하여 표면에너지를 87 $mJ/m^2$로 높임으로써 표면에너지 차이를 극대화 하였다. G-PEDOT:PSS 전도성 고분자를 브러쉬 인쇄공정으로 소스/드레인 전극 영역 주변에 도포하여 전극을 성형하였으며, OTFT 어레이 ($16{\times}16$)에서 약 90% 가까운 수율을 나타내었다. 불소계 화합물을 첨가한 PVP와 펜타센 반도체를 사용한 OTFT의 성능은 첨가하지 않은 소자와 비교하여 큰 차이가 없었으며, 이동도는 0.1 $cm^2/V.sec$ 로서 전기영동디스플레이(EPD) 시트를 구동하기에 충분한 성능이었다. OTFT 어레이에 EPD 시트를 부착하여 성공적인 작동을 확인하였다.

• 한국자기학회지
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• 제14권4호
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• pp.131-137
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• 2004

이동통신주파수 대역에서 박형의 전파흡수체를 제작하기 위해 순철 분말을 흡수 충진재로 사용한 고무 복합체의 고주파 특성(복소투자율, 복소유전율) 및 전파흡수특성에 대해 조사하였다. 주요 실험변수는 순철 분말의 초기입도와 형상(구형, 압분체) 변화였다. Attrition milling에 의해 두께가 표피두께보다 작은 순철 압분체를 제작함으로써 임피던스정합 조건에 근접하는 고투자율과 고유전율을 동시에 얻을 수 있었다. 이는 milling에 의해 구형에서 평판상으로 모양이 바뀜에 따라 와전류 손실이 감소하고(복소투자율의 증가), 압분체 간의 정전용량이 증가한 것(복소유전율의 증가)에 기인한다. 초기입도가 10$\mu\textrm{m}$인 순철 압분체를 흡수 충진재로 사용함으로써 이동통신주파수 대역(0.8-2.0㎓)에서 반사손실이 -5㏈(70% 전력흡수율), 두께가 0.7mm 수준인 박형의 전파흡수체를 제안할 수 있었다.