• Title/Summary/Keyword: Hierarchical QoS routing

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A QoS Guaranteed Mechanism Using the FRSVP in the Hierarchical Mobile IPv6 (계층적 이동 IPv6 네트워크에서 FRSVP를 이용한 QoS 보증 방안)

  • Kim Bo-Gyun;Hong Choong-Seon;Lee Dae-Young
    • The KIPS Transactions:PartC
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    • v.12C no.3 s.99
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    • pp.419-428
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    • 2005
  • This paper divides domains into the intra, inter domain according to the mobile node's movement and .proposes the Fast RSVP algorithm on the HMIPv6. It is done to advance reservation using L2 beacon signal when MN is located to overlapped cell area. In case of intra-region handoff, the advance reservation is reserved at the nearest common router and In case of inter-region handoff, it is done to advance reservation through the other site MAP's QA(QoS Agent) to the AR and optimize CN's path. Because of using the bandwidth efficiently and switching the data path quickly, the proposal algorithm minimizes the service disruption by data routing.

Hierarchical Binary Search Tree (HBST) for Packet Classification (패킷 분류를 위한 계층 이진 검색 트리)

  • Chu, Ha-Neul;Lim, Hye-Sook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.3B
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    • pp.143-152
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    • 2007
  • In order to provide new value-added services such as a policy-based routing and the quality of services in next generation network, the Internet routers need to classify packets into flows for different treatments, and it is called a packet classification. Since the packet classification should be performed in wire-speed for every packet incoming in several hundred giga-bits per second, the packet classification becomes a bottleneck in the Internet routers. Therefore, high speed packet classification algorithms are required. In this paper, we propose an efficient packet classification architecture based on a hierarchical binary search fee. The proposed architecture hierarchically connects the binary search tree which does not have empty nodes, and hence the proposed architecture reduces the memory requirement and improves the search performance.

Traffic Engineering Based on Local States in Internet Protocol-Based Radio Access Networks

  • Barlow David A.;Vassiliou Vasos;Krasser Sven;Owen Henry L.;Grimminger Jochen;Huth Hans-Peter;Sokol Joachim
    • Journal of Communications and Networks
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    • v.7 no.3
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    • pp.377-384
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    • 2005
  • The purpose of this research is to develop and evaluate a traffic engineering architecture that uses local state information. This architecture is applied to an Internet protocol radio access network (RAN) that uses multi-protocol label switching (MPLS) and differentiated services to support mobile hosts. We assume mobility support is provided by a protocol such as the hierarchical mobile Internet protocol. The traffic engineering architecture is router based-meaning that routers on the edges of the network make the decisions onto which paths to place admitted traffic. We propose an algorithm that supports the architecture and uses local network state in order to function. The goal of the architecture is to provide an inexpensive and fast method to reduce network congestion while increasing the quality of service (QoS) level when compared to traditional routing and traffic engineering techniques. We use a number of different mobility scenarios and a mix of different types of traffic to evaluate our architecture and algorithm. We use the network simulator ns-2 as the core of our simulation environment. Around this core we built a system of pre-simulation, during simulation, and post-processing software that enabled us to simulate our traffic engineering architecture with only very minimal changes to the core ns-2 software. Our simulation environment supports a number of different mobility scenarios and a mix of different types of traffic to evaluate our architecture and algorithm.

Performance Analysis about the Failure Restoration Scheme Using a Multi-path in Hierarchical MPLS Networks (계층형 MPLS 네트워크에서 다중 경로를 이용한 장애 복구 방안에 관한 성능 분석)

  • Jang, Seong-Jin;Kim, Ki-Yong;Jang, Jong-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.06a
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    • pp.61-64
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    • 2007
  • MPLS networks architectures have been prevailed as scalable approach to provide quality of service in the Internet. Many researches have been mainly focused on scalability and multi-path calculation scheme for failure restoration. However, the MPLS network have an scalability problem about traffic, and the existing failure restoration methods are wasted resources, and it has the problem that loss of a packet by a lot of delay occurs in too. Therefore in this paper, we propose a H-MPLS (Hierachical-Multiprotocol Label Switching)network for rapidly failure restorations and effective management of network extended. The proposed H-MPLS Network apply LSP multi-path routing algorithm and consists of several MPLS. After comparing the performance among the existing failure restoration methods with various network models, we use NS simulator in order to analyze the performance. Finally, we present an improvement scheme of the efficiency and scalability.

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Simulation Analysis for Verifying an Implementation Method of Higher-performed Packet Routing

  • Park, Jaewoo;Lim, Seong-Yong;Lee, Kyou-Ho
    • Proceedings of the Korea Society for Simulation Conference
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    • 2001.10a
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    • pp.440-443
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    • 2001
  • As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

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