• Title/Summary/Keyword: Height of barrier

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Improvement plan for the standard for calculating the height of the stair railing for Barrier Free (BF) certification system (장애물 없는 생활환경(BF) 인증제도 계단 난간 높이 산정기준 개선안)

  • Lee, Sang-Soo;Bang, Hong-Soon;Kim, Ok-Kyue
    • Proceedings of the Korean Institute of Building Construction Conference
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    • 2022.04a
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    • pp.218-219
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    • 2022
  • Among the Barrier Free (BF) certification evaluation items for public facilities, at which position the standard for the effective height of the stair railing handle should be calculated is not clearly determined. Because of this, not only the evaluation standards of the certification authority and the evaluation committee are different, but disputes are occurring between the ordering organization, the design company, and the construction company. Therefore, the stair railing installation standard laws for public facilities were analyzed and through a case study of institutions that obtained the BF certification, problems were analyzed. The results of problem analysis reveal the following. 1) The standards of the Ministry of Health and Welfare and the Ministry of Land, Infrastructure, and Transport were different. 2) The effective height calculation standard was ambiguous, and disputes occurred frequently. To solve this problem, we proposed improvement plans for calculating the height of the stair railing that can comply with laws while ensuring safety.

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Variations of Interface Potential Barrier Height and Leakage Current of (Ba, Sr)$TiO_3$ Thin Films Deposited by Sputtering Process

  • Hwang, Cheol-Seong;Lee, Byoung-Taek
    • The Korean Journal of Ceramics
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    • v.2 no.2
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    • pp.95-101
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    • 1996
  • Variations of the leakage current behaviors and interface potential barrier $({\Phi}_B)$ of rf-sputter deposited (Ba, Sr)$TiO_3$ (BST) thin films with thicknesses ranging from 20 nm to 150nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. ${\Phi}_B$ critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under $N_2$ atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the ${\Phi}_B$ from about 2.4 eV to 1.6 eV due to the oxidation. ${\Phi}_B$ is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20 nm thick film shows tunneling current, 30 and 40 nm thick films show Shottky emission current.

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Electrical Characteristics of Metal/n-InGaAs Schottky Contacts Formed at Low Temperature

  • 이홍주
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.5
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    • pp.365-370
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    • 2000
  • Schottky contacts on n-In$\_$0.53//Ga$\_$0.47//As have been made by metal deposition on substrates cooled to a temperature of 77K. The current-voltage and capacitance-voltage characteristics showed that the Schottky diodes formed at low temperature had a much improved barrier height compared to those formed at room temperature. The Schottky barrier height ø$\_$B/ was found to be increased from 0.2eV to 0.6eV with Ag metal. The saturation current density of the low temperature diode was about 4 orders smaller than for the room temperature diode. A current transport mechanism dominated by thermionic emission over the barrier for the low temperature diode was found from current-voltage-temperature measurement. Deep level transient spectroscopy studies exhibited a bulk electron trap at E$\_$c/-0.23eV. The low temperature process appears to reduce metal induced surface damage and may form an MIS (metal-insulator-semiconductor)-like structure at the interface.

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Experimental and Simulation Study of Barrier Properties in Schottky Barrier Thin-Film Transistors with Cr- and Ni- Source/Drain Contacts (Cr- 및 Ni- 소스/드레인 쇼트키 박막 트랜지스터의 장벽 특성에 대한 실험 및 모델링 연구)

  • Jung, Ji-Chul;Moon, Kyoung-Sook;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.10
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    • pp.763-766
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    • 2010
  • By improving the conducting process of metal source/drain (S/D) in direct contact with the channel, schottky barrier metal-oxide-semiconductor field effect transistors (SB MOSFETs) reveal low extrinsic parasitic resistances, offer easy processing and allow for well-defined device geometries down to the smallest dimensions. In this work, we investigated the arrhenius plots of the SB MOSFETs with different S/D schottky barrier (SB) heights between simulated and experimental current-voltage characteristics. We fabricated SB MOSFETs using difference S/D metals such as Cr (${\Phi}_{Cr}$ ~4.5 eV) and Ni (${\Phi}_{Ni}$~5.2 eV), respectively. Schottky barrier height (${\Phi}_B$) of the fabricated devices were measured to be 0.25~0.31 eV (Cr-S/D device) and 0.16~0.18 eV (Ni-S/D device), respectively in the temperature range of 300 K and 475 K. The experimental results have been compared with 2-dimensional simulations, which allowed bandgap diagram analysis.

Characteristics of Schottky Diode and Schottky Barrier Metal-Oxide-Semiconductor Field-Effect Transistors

  • Jang, Moon-Gyu;Kim, Yark-Yeon;Jun, Myung-Sim;Lee, Seong-Jae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.2
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    • pp.69-76
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    • 2005
  • Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

Effect of Double Noise-Barrier on Air Pollution Dispersion around Road, Using CFD

  • Jeong, Sang Jin
    • Asian Journal of Atmospheric Environment
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    • v.8 no.2
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    • pp.81-88
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    • 2014
  • Noise-barriers on both sides of the roadway (hereafter referred to as double noise-barriers), are a common feature along roads in Korea, and these are expected to have important effects on the near-road air pollution dispersion of vehicle emissions. This study evaluated the double noise-barrier impact on near-road air pollution dispersion, using a FLUENT computational fluid dynamics (CFD) model. The realizable k-${\varepsilon}$ model in FLUENT CFD code was used to simulate vehicle air pollutant dispersion, in around 11 cases of double noise-barriers. The simulated concentration profiles and surface concentrations under no barrier cases were compared with the experimental results. The results of the simulated flows show the following three regimes in this study: isolated roughness (H/W=0.05), wake interface (H/W=0.1), and skimming flow (H/W>0.15). The results also show that the normalized average concentrations at surface (z=1 m) between the barriers increase with increasing double noise-barrier height; however, normalized average concentrations at the top position between the barriers decrease with increasing barrier height. It was found that the double noise-barrier decreases normalized average concentrations of leeward positions, ranging from 0.8 (H/W=0.1, wake interface) to 0.1 (H/W=0.5, skimming flow) times lower than that of the no barrier case, at 10 x/h downwind position; and ranging from 1.0 (H/W=0.1) to 0.4 (H/W=0.5) times lower than that of the no barrier case, at 60 x/h downwind position.

Analysis of Thermal Stability and Schottky Barrier Height of Pd Germanide on N-type Ge-on-Si Substrate (N형 Ge-on-Si 기판에 형성된 Pd Germanide의 열안정성 및 Schottky 장벽 분석)

  • Oh, Se-Kyung;Shin, Hong-Sik;Kang, Min-Ho;Bok, Jeong-Deuk;Jung, Yi-Jung;Kwon, Hyuk-Min;Lee, Ga-Won;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.4
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    • pp.271-275
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    • 2011
  • In this paper, thermal stability of palladium germanide (Pd germanide) is analyzed for high performance Schottky barrier germanium metal oxide semiconductor field effect transistors (SB Ge-MOSFETs). Pd germanide Schottky barrier diodes were fabricated on n-type Ge-on-Si substrates and the formed Pd germanide shows thermal immunity up to $450^{\circ}C$. The barrier height of Pd germanide is also characterized using two methods. It is shown that Pd germanide contact has electron Schottky barrier height of 0.569~0.631 eV and work function of 4.699~4.761 eV, respectively. Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.

Development of a Flow Sensor Using DBD (Dielectric Barrier Discharge) (DBD (Dielectric Barrier Discharge)를 이용한 유량 센서 개발에 관한 연구)

  • Kim, Tae-Hoon;Kim, Sung-Jin
    • Proceedings of the KSME Conference
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    • 2008.11b
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    • pp.2076-2081
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    • 2008
  • In this study, a new concept of a flow sensor is developed using dielectric barrier discharge (DBD). Current of DBD generated between two electrodes is changed with varying flow rates. Therefore, it is possible to measure the flow rate by correlating generated DBD current with flow rates. The effects of flow rate, frequency, channel height, diameter of electrodes and distance between electrodes on the performance of the flow sensor using DBD are experimentally investigated.

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Effects of floating wave barriers on wave-induced forces exerted to offshore-jacket structure

  • Osgouei, Arash Dalili;Poursorkhabi, Ramin Vafaei;Hosseini, Hamed;Qader, Diyar N.;Maleki, Ahmad;Ahmadi, Hamid
    • Structural Engineering and Mechanics
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    • v.83 no.1
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    • pp.53-66
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    • 2022
  • The main objective of the present research was investigating the effects of a floating wave barrier installed in front of an offshore jacket structure on the wave height, base shear, and overturning moment. A jacket model with the height of 4.55 m was fabricated and tested in the 402 m-long wave flume of NIMALA marine laboratory. The jacket was tested at the water depth of 4 m subjected to the random waves with a JONSWAP energy spectrum. Three input wave heights were chosen for the tests: 20 cm, 23 cm, and 28 cm. Two different cross sections with the same area were selected for the wave barrier: square and rhombus. Results showed that the average decrease in the jacket's base shear due to the presence of a floating wave barrier with square and rhombus cross section was 24.67% and 34.29%, respectively. The use of wave barriers with square and rhombus cross sections also resulted in 19.78% and 33.11% decrease in the jacket's overturning moment, respectively. Hence, it can be concluded that a floating wave barrier can significantly reduce the base shear and overturning moment in an offshore jacket structure; and a rhombus cross section is more effective than an equivalent square section.

The relationship between addressing time and dielectric layer, barrier rib hight (AC PDP의 addressing time과 유전체 및 Barrier Rib 높이와의 상관관계)

  • Park, J.T.;Park, C.S.;Song, K.D.;Park, C.H.;Cho, J.S.
    • Proceedings of the KIEE Conference
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    • 2000.07c
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    • pp.1824-1826
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    • 2000
  • Up to date, the dual scanning method has been adopted to decrease address-ing period in AC PDP. In this case, addressing period can be reduced, but the driving circuit cost should be increased. In this study, to increase addressing speed we have studied the relationship between addressing speed and cell structure. That is to say, we varied the thickness of dielectric layer on the front glass, the thickness of white back and the height of barrier rib on the rear glass. So, we found that the addressing time was decreased 4% with decreasing 5um thickness of dielectric layer on the front glass and 2um thickness of white back on the rear glass. Also in case of decreasing the height of barrier rib, addressing time was decreased about 4% per 10um.

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