• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.749-757
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• 2015

As the smart era, the use of smart devices is increasing. Smart devices are widely used to provide a human convenience, but there is a risk that information is exposed. The smart devices to prevent this problem includes the encryption algorithm. Among them, The hash function is an encryption algorithm that is used essentially to carry out the algorithm, such as data integrity, authentication, signature. As the issue raised in the collision resistance of SHA-1 has recently been causing a safety problem, and SHA-1 hash function based on the current standard of SHA-2 would also be a problem in the near future safety. Accordingly, NIST selected KECCAK algorithm as SHA-3, it has become necessary to implement this in various environments for this algorithm. In this paper, implementation of KECCAK algorithm. And SHA-2 On The ARM-11 processor, and compare performance.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2002.11a
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• pp.211-214
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• 2002

본 논문에서는 loop unrolling 방법을 적용한 해쉬 함수의 하드웨어 구현에 관하여 기술한다. 해쉬 함수는 메시지의 무결성을 보장하기 위한 인증에 사용되는 알고리즘으로 메시지를 처리하는 전처리부, 데이터 압축을 수행하는 반복 프로세싱부, 그리고 처리된 결과를 출력하는 결과 출력부로 기능을 분리할 수 있다. 이때 데이터 연산 처리 속도를 개선하기 위하여 반복 프로세싱부에 loop unrolling 기법을 적용하였다. 본 논문에서는 loop unrolling 기법을 적용한 해쉬 함수의 구현에 관한 것과 이로 인한 성능 개선 효과에 대하여 기술한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.04a
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• pp.459-460
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• 2017

해시 함수는 데이터의 위변조를 확인하기 위해 사용하는 일방향 함수로, 현재 많은 기술 및 논문에서 해시 함수를 사용하고 있다. 대표적인 해시 함수에는 MD와 SHA가 있으며 다양한 버전을 가지고 있다. 본 논문에서는 해시 알고리즘들의 안전성과 관련된 동향과 취약점을 파악하고 향후 방향성을 알아보고자 한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.263-266
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• 2012

This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.81-88
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• 2013

Since nowadays mobile phone messages are flourishing, the application of electronic coupon (e-coupon) will become a trend for mobile users. E-coupon for mobile commerce can provide mobility for users and distribution flexibility for issuers. In this paper, we propose a mobile e-coupon system that just applies some simple cryptographic techniques, such as one-way hash function and XOR operation. In our system, the customer can control the number of issued e-coupons and the issuer can prevent them from double-redeeming. The customer does not need to perform any exponential computation in redeeming and transferring the coupons. Our scheme uses one-way hash chains for preventing from double-spending.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.63-65
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• 2021

This paper describes an integrated H/W-S/W implementation of elliptic curve digital signature algorithm (EC-DSA) using a security system-on-chip (SoC). The security SoC uses the Cortex-A53 APU as CPU, and the hardware IPs of high-performance elliptic curve cryptography (HP-ECC) core and SHA3 (secure hash algorithm 3) hash function core are interfaced via AXI4-Lite bus protocol. The signature generation and verification processes of EC-DSA were verified by the implementation of the security SoC on a Zynq UltraScale+ MPSoC device.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2256-2270
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• 1998

The development of a high perfoffilance index system is crucial for the retrieval of information from large sets o[ data. In this study, a minimal perfect hash function (MPHF), which hashes m keys to m buckets with no collisions, is revisited. The MOS algorithm developed bv Heath is modified to be successful for computing MPHFs of large sets of keys Also, a system for generating MPHFs for large sets of keys is developed. This system computed MPHFs for several large sets of data more efficiently than Heath's. The application areas for this system include those for generating MPHFs for the indexing of large and infrequently changing sets of data as well as information stored in a medium whose seek time is very slow.

• Journal of KIISE:Information Networking
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• v.32 no.4
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• pp.462-470
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• 2005

A hash chain is highly efficient and attractive structure to use in electronic cash. Previous systems using hash chain are used extensively in various cryptography applications such as one-time passwords, server-supported signatures and microments. However, The most hash chain based systems using fro-paid method provide anonymity but have the problem to increase payment cost. Therefore, in this paper, we propose a new hash chain based microment system which improves efficiency using session key and guarantees user anonymity through blind signature in the withdrawal process of the root value without disclosing privacy Information.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.166-168
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• 2018

본 논문에서는 Whirlpool 해시 코어가 Cortex-M0의 슬레이브로 인터페이스된 보안 SoC 프로토타입 구현에 대해 기술한다. ISO/IEC에서 표준으로 채택된 경량 해시 알고리듬인 Whirlpool 해시 함수를 64-비트의 데이터 패스로 구현하였으며, 키 확장 연산과 암호화 연산을 수행하는 하드웨어를 공유하여 면적이 최소화되도록 설계하였다. 설계된 보안 SoC 프로토타입을 Cyclone-V FPGA에 구현한 후, ULINK2 어댑터와 Cortex 내부 디버거를 통해 Whirlpool 해시 코어에서 연산된 해시값을 확인함으로써 SoC 프로토타입의 동작을 확인했다.