• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.142-153
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• 2021

Recent research on synaptic devices has been reviewed from the perspective of hardware-based neuromorphic computing. In addition, the backgrounds of neuromorphic computing and two training methods for hardware-based neuromorphic computing are described in detail. Moreover, two types of memristor- and CMOS-based synaptic devices were compared in terms of both the required performance metrics and low-power applications. Based on a review of recent studies, additional power-scalable synaptic devices such as tunnel field-effect transistors are suggested for a plausible candidate for neuromorphic applications.

• Electronics and Telecommunications Trends
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• v.35 no.4
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• pp.34-41
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• 2020

The existing Von Neumann architecture places limits to data processing in AI, a booming technology. To address this issue, research is being conducted on computing architectures and artificial neural networks that simulate neurons and synapses, which are the hardware of the human brain. With high-speed, high-throughput data communication infrastructures, photonic solutions today are a mature industrial reality. In particular, due to the recent outstanding achievements of artificial neural networks, there is considerable interest in improving their speed and energy efficiency by exploiting photonic-based neuromorphic hardware instead of electronic-based hardware. This paper covers recent photonic neuromorphic studies and a classification of existing solutions (categorized into multilayer perceptrons, convolutional neural networks, spiking neural networks, and reservoir computing).

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.5
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• pp.71-77
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• 2021

Recently, there is a demand for efficient program development of an IoT application support frameworks considering heterogeneous hardware characteristics. In addition, the scope of hardware support is expanding with the development of neuromorphic architecture that mimics the human brain to learn on their own and enables autonomous computing. However, most existing IoT IDE(Integrated Development Environment), it is difficult to support AI(Artificial Intelligence) or to support services combined with various hardware such as neuromorphic architectures. In this paper, we design an AI component abstract model that supports the second-generation ANN(Artificial Neural Network) and the third-generation SNN(Spiking Neural Network), and implemented an autonomous IoT IDE based on the proposed model. IoT developers can automatically create AI components through the proposed technique without knowledge of AI and SNN. The proposed technique is flexible in code conversion according to runtime, so development productivity is high. Through experimentation of the proposed method, it was confirmed that the conversion delay time due to the VCL(Virtual Component Layer) may occur, but the difference is not significant.

• The Journal of the Convergence on Culture Technology
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• v.8 no.5
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• pp.613-618
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• 2022

Research on artificial intelligence based on SNN (Spiking Neural Networks) is drawing attention as a next-generation artificial intelligence that can overcome the limitations of artificial intelligence based on DNN (Deep Neural Networks) that is currently popular. In this paper, we describe the structure of the SNN compiler, a system SW that generate code from SNN description for neuromorphic computing systems. We also introduce the algorithms used for compiler implementation and present experimental results on how the execution time varies in neuromorphic computing systems depending on the the mapping algorithm. The mapping algorithm proposed in the text showed a performance improvement of up to 3.96 times over a random mapping. The results of this study will allow SNNs to be applied in various neuromorphic hardware.

• Ceramist
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• v.21 no.2
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.4
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• pp.311-321
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• 2022

The report reviews recent research efforts in demonstrating a computing system whose operation principle mimics the dynamics of biological neurons. The temporal variation of the membrane potential of neurons is one of the key features that contribute to the information processing in the brain. We first summarize the neuron models that explain the experimentally observed change in the membrane potential. The function of ion channels is briefly introduced to understand such change from the molecular viewpoint. Dedicated circuits that can simulate the neuronal dynamics have been developed to reproduce the charging and discharging dynamics of neurons depending on the input ionic current from presynaptic neurons. Key elements include volatile memristors that can undergo volatile resistance switching depending on the voltage bias. This behavior called the threshold switching has been utilized to reproduce the spikes observed in the biological neurons. Various types of threshold switch have been applied in a different configuration in the hardware demonstration of neurons. Recent studies revealed that the memristor-based circuits could provide energy and space efficient options for the demonstration of neurons using the innate physical properties of materials compared to the options demonstrated with the conventional complementary metal-oxide-semiconductors (CMOS).