• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.352-359
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• 2008

This paper presents a controller implementation using model based controller design programs-System Identification Toolkit, Control Design Toolkit, Simulation module. This method is easier and simpler than conventional controller design method. To implement speed control system of DC motor, a CompactRIO, Real-Time(RT) cntroller provided by NI(National Instruments), is used as hardware equipment. Firstly transfer function of DC motor drive system, which was a control target plant, can be acquired through System Identification Toolkit by using test input signal applied to motor and output signal from motor. And designing of pole-zero compensator satisfying desired control response performance through Control Design Toolkit, designed speed control response can be tested through Simulation Module. Finally LabVIEW program is converted to real-time program and downloaded to CompactRIO real-time controller Through experimental results to real DC motor drive system, designed speed control response is compared to simulation results.

• Journal of the Korean Society for Nondestructive Testing
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• v.30 no.4
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• pp.338-344
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• 2010

A double rotation C-scanning system and a software program Under-Sodium MultiVIEW have been developed for the under-sodium viewing of a reactor core and in-vessel structures of a sodium-cooled fast reactor KALIMER-600. Double rotation C-scanning system has been designed and manufactured by the reproduction of double rotation plug of a reactor head in KALIMER-600. Hardware system which consists of a double rotating scanner, ultrasonic waveguide sensors, a high power ultrasonic pulser-receiver, a scanner driving module and a multi channel A/D board have been constructed. The functions of scanner control, image mapping and signal processing of Under-Sodium MultiVIEW program have been implemented by using a LabVIEW graphical programming language. The performance of Under-Sodium MultiVIEW program was verified by a double rotation C-scanning test in water.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.1
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• pp.110-115
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• 2006

STSAT-2 is the first satellite which will be launched by the first Korean Space Launch Vehicle(KSLV). Ground station Baseband Control system(GBC) is now developed for STSAT-2. GBC has two functions. One is control data path between satellite control computers and ground station antennas(1.5M, 3.7M, 13M) automatically. The other is sending and receiving data between ground station and satellite. GBC is implemented by FPGA(Field-Programmable Gate Array) which includes almost all logic(for MODEM, PROTOCOL and GBC system control). MODEM in GBC has two uplink FSK modulators(1.2[kbps], 9.6[kbps]) and six downlink FSK demodulators(9.6[kbps], 38.4[kbps]). In hardware, STSAT-2 GBC is smaller than STSAT-1 GBC. In function, STSAT-2 GBC has more features than STSAT-1 GBC. This paper is about GBC structure, functions and test results.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.685-695
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• 2002

Recently, there has been increasingly demand for connecting a embedded device to the Internet. Jini technology is interested in automatically composing a distributed network with devices But, there are some problems that the device needs high hardware requirements to adopt Jini technology for supporting Jini-enabled services. In this paper, we focused on design and implementation of surrogate system that supports non-Java devices in Jini networks. This system and protocol are implemented in Java language. The surrogate system delegates Discovery and Join processing to support a Jini service in connected networks. A Jini client can use service of the device through the surrogate system. We tested a Jini sample program to verify the implemented surrogate system. In the test result, we showed that the Jini client can use functionalities and operations of the non-Java device through the surrogate system.

• Journal of Engineering Education Research
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• v.11 no.3
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• pp.63-69
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• 2008

This study provides a program to promote effective project instruction. With a 4 step learning model as preparation, planning, implementation and evaluating it was adapted to a course of study in automobile electricity fields of college. The purpose of this study was to document project process from the learner's point of view and examine the effect of project instruction with recognition of learner who has completed a course of project study. The data from 28 learner in hardware and software automobile electricity fields of college were collected and interpreted statistically by t-test at the .05 level of significance. It was concluded as follows. It emphasizes the importance not only of motivating active group effort and cooperative relationship between group members, but also communication with presentation in order to have a successful accomplishment of a project.

• Ceramist
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• v.21 no.2
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• KIISE Transactions on Computing Practices
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• v.21 no.3
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• pp.173-182
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• 2015

Motion control systems are widely deployed in various industrial automation processes. The motion controller, which is a key element of motion control systems, has stringent real-time constraints. The controller must provide a short and deterministic control message transmission cycle, and minimize the actuation deviation among motor drives. To meet these requirements, hardware-based proprietary controllers have been prevalent. However, since it is becoming difficult for such an approach to meet increasing needs of system interoperability and scalability, nowadays, software-based universal motion controllers are regarded as their substitutes. Recently, embedded motion controller solutions are gaining attention due to low cost and relatively high performance. In this paper, we designed and implemented an embedded motion controller on an ARM-based evaluation board by using Xenomai real-time kernel and other open source software components. We also measured and analyzed the performance of our embedded controller under a realistic test-bed environment. The experimental results show that our embedded motion controller can provide relatively deterministic performance with synchronized control of three motor axis at 2 ms control cycle.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.5 no.4
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• pp.47-63
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• 1994

An important parameter in characterizing mobile communication channel is delay spread. This paper presents the results of measured delay profiles and calculated distribution funcations of delay spread for typical cellular service environments at Taejon and vicinities. The measurement system uses 1023 chip length, 5 Mbps PN code and sliding correlation method. It has been evaluated by using commercial hardware channel simulator for reliability of out data. As results the value of mean delay spread is 2.08 $\mu\textrm{s}$for suburban area. 2.12 $\mu\textrm{s}$ for urban area and 1.3 $\mu\textrm{s}$ for national/local road. Delay spread is less then 3.4$\mu\textrm{s}$, 2.8$\mu\textrm{s}$ and 1.5 $\mu\textrm{s}$ for probability of 50% and 4.5$\mu\textrm{s}$, 4.2$\mu\textrm{s}$ and 2.9$\mu\textrm{s}$ for probability of 90% at each tested site. The difference of delay spread is within 7% between going and returning status along same street. In this experiment, we found delay spread for suburban area is larger than reported foreign test results.