• 디지털산업정보학회논문지
• /
• 제19권2호
• /
• pp.69-78
• /
• 2023

In this paper, IO+5G dedicated hardware is developed and an AI device communication system equipped with a 5G is designed and tested. The AI device communication system equipped with a 5G receives the collected real-time images and the information collected from the IoT sensor in real time is to analyze the information and generates the risk detection events in the AI processing board. The event generated in the AI processing board creates a 5G channel in the dedicated hardware equipped with IO+5G. The created 5G channel delivers event video to the control video server. The 5G based dongle network enables faster data collection and more precise data measurement compared to wireless LAN and 5G routers. As a result of the experiment in this paper, the average test result of the 5G dongle network is about 51% faster than the Wi-Fi average test result in downlink and about 40% faster in uplink. In addition, when comparing the test result with terms of the 5G rounter to be set to 80% upload and 20% download, the average test result is that the 5G dongle network is about 11.27% faster when downloading and about 17.93% faster when uploading. when comparing the test result with terms of the the router to be set to 60% upload and 40% download, the 5G dongle network is about 11.19% faster when downlinking and about 13.61% faster when uplinking. Therefore, in this paper it describes that the developed 5G dongle network can improve the results by collecting data and analyzing it faster than wireless LAN and 5G routers.

• 대한전자공학회논문지
• /
• 제22권1호
• /
• pp.7-13
• /
• 1985

쉽게 시험할 수 특성을 가진 SLA 의 설계에 관해 논하였다. 제안된 SLA는 hardware를 부가함으로써 회로의 상태를 쉽게 조절하고 점검할 수 있게 하였다. 제안된 SLA는 test pattern과 응답이 SLA에 구현된 함수에 관계없고 단지 SLA의 크기에 따라 유일하게 결정되는 매우 짧은 보편적인 test sequence를 갖는다. 여기서 고려된 SLA의 고장은 단일 및 다중 stuck faults, crosspoint faults 및 bridge faults이다. 또한 고장의 위치 판별 및 그 처리에 관해서도 고찰하였다.

• 대한전자공학회논문지SD
• /
• 제41권11호
• /
• pp.87-95
• /
• 2004

본 논문에서는 SoC 테스트를 위한 새로운 테스트 데이터 압축 방법을 제안한다. 제안하는 압축 방법은 테스트 데이터 압축을 위해 압축율과 하드웨어 오버헤드를 고려하여 최대 효율을 가지도록 하는데 기초하고 있다. 압축율을 높이기 위해서 본 논문에서는 IR 기법과 MSCIR 압축 코드를 사용하며, 뿐만아니라 이를 위한 사전 작업인 새로운 맵핑 기법 및 테스트 패턴순서 재조합 방법을 제안한다. 기존의 연구와는 달리 CSR 구조를 사용하지 않고 원래의 테스트 데이터를 사용하여 압축하는 방법을 사용한다. 이렇게 함으로써 제안하는 압축 방법은 기존의 연구에 비해 훨씬 높은 압축율을 가지며 낮은 하드웨어 오버헤드의 디컴프레션 구조를 가진다. ISCAS '89 벤치 회로에 대한 기존의 연구와의 비교로서 그 결과를 알 수 있다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2009년도 제40회 하계학술대회
• /
• pp.1047_1048
• /
• 2009

This paper describes comparative analysis results about the dynamic interaction of interconnected wind power system using the actual-size hardware simulator and the simulation model with PSCAD/EMTDC. The hardware simulator, which is composed of 2.0MVA induction motor with drive system and 1.5MW doubly-fed induction generator, was built and tested in Go-Chang Test Site of KEPCO for analyzing the dynamic interaction with the interconnected distribution system. The operation of hardware simulator was verified through comparative analysis between experimental results and simulation results obtained by simulation model with PSCAD/EMTDC. The developed hardware simulator and simulation model could be effectively used for analyzing the dynamic interaction, which has various phenomena depending on the wind variation and the network state of interconnected power system.

• 전기학회논문지P
• /
• 제58권3호
• /
• pp.263-269
• /
• 2009

This paper describes comparative analysis results about the dynamic interaction of interconnected wind power system using the actual-size hardware simulator and the simulation model with PSCAD/EMTDC. The hardware simulator, which is composed of 2.0MVA induction motor with drive system and 1.5MW doubly-fed induction generator, was built and tested in Go-Chang Test Site of KEPCO for analyzing the dynamic interaction with the interconnected distribution system. The operation of hardware simulator was verified through comparative analysis between experimental results and simulation results obtained by simulation model with PSCAD/EMTDC. The developed hardware simulator and simulation model could be effectively used for analyzing the dynamic interaction, which has various phenomena depending on the wind variation and the network state of interconnected power system.

• 전기학회논문지P
• /
• 제67권1호
• /
• pp.9-14
• /
• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• 대한임베디드공학회논문지
• /
• 제3권1호
• /
• pp.19-24
• /
• 2008

To reduce time-to-market, more and more embedded system developers and system-on-chip designers rely on microprocessor-based design methodology. ARM processor has been a major player in this industry over the last 10 years. However, there are many restrictions on developing embedded software using ARM processor in the early design stage. For those who are not familiar with embedded software development environment or who cannot afford to have an expensive embedded hardware equipment, testing their software on a real ARM hardware platform is a challenging job. To overcome such a problem, we have designed VMA (Virtual ARM Machine), which offers easier testing and debugging environment to ARM based embedded system developers. Major benefits that can be achieved by utilizing a virtual ARM platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. Unlike many other purely software-oriented ARM simulators which are independent of real hardware platforms, VMA is specifically targeted on SYS-Lab 5000 ARM hardware platform, (designed by Libertron, Inc.), which means that VMA imitates behaviors of embedded software as if the software is running on the target embedded hardware as closely as possible. This paper will describe how VMA is designed and how VMA can be used to reduce design time and cost.

• Journal of Platform Technology
• /
• 제6권4호
• /
• pp.26-33
• /
• 2018

In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.

• 전자공학회논문지
• /
• 제51권11호
• /
• pp.187-192
• /
• 2014

카메라와 같이 연속적인 영상을 제공하는 환경에서 특징 점들을 추출하기 위해 다양한 알고리즘들이 연구되고 있다. 특히, FAST (Feature from Accelerated Segment Test) 알고리즘은 연산 구조가 간단하고 실시간 특징 점 추출이 용이하여 FPGA 기반 하드웨어 가속기로 구현되어 사용되고 있다. 사용된 FAST 하드웨어 가속기는 특징 점을 추출하기 위해 임계값을 필요로 한다. 임계값은 영상에서 추출되는 특징 점의 기준이 되는 값으로, 값의 크기에 따라 추출되는 특징 점의 개수가 정해질 뿐만 아니라 전체 수행시간에도 영향을 주기 때문에, 일정한 수행시간 동안에 많은 특징 점들을 추출하기 위해서는 적절한 임계값 제어 방법이 요구된다. 본 논문에서는 임계값 제어를 위해 PI 제어기를 제안한다. 제안한 PI 제어기는 시험 영상들을 통해 기능 및 성능을 검증하였고, Xilinx Vertex IV FPGA 기반의 로직으로 구현 비용을 계산하였다. 제안한 PI 제어기는 47개의 Flip Flops, 146개의 LUTs, 그리고 91개의 Slices을 사용해, FAST 하드웨어 가속기 2.1%의 Flip Flop, 4.4%의 LUTs, 그리고 4.6%의 Slice에 해당하는 적은 비용으로 구현되었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1983년도 하계학술회의강연.논문초록집
• /
• pp.203-205
• /
• 1983