• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1714-1719
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• 2003

Antilock Brake System (ABS) is indispensable safety equipment for vehicles today. In order to develop new ABS ECU suitable for pneumatic brake system of a bus, a Hardware In-the-Loop Simulation (HILS) System was developed. In this HILS, the pneumatic brake system of a bus and antilock brake component were used as hardware. For the computer simulation, the 14-Degree of Freedom (DOF) bus dynamic model was constructed using the Matlab/Simulink software package. This model was compiled and downloaded in the simulation board, where the Power PC processor was used for real-time simulation. Additional commercial package, the ControlDesk was used to monitor the dynamic simulation results and physical signal values. This paper will focus on the procedure and results of evaluating the ECU in the HILS simulation. Two representative cases, wet basalt road and $split-{\mu}$ road, were used to simulate real road conditions. At each simulated road, the vehicle was driven and stopped under the help of the developed ECU. In each simulation, the dynamical behavior of the vehicle was monitored. After enough tests in the laboratory using HILS, the parameter-tuned ECU was equipped in a real bus, which was driven and stopped in the real test field in Korea. And finally, the experiment results of ABS equipped vehicle's dynamic behavior both in HILS test and in test fields were compared.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.6
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• pp.547-558
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• 2008

Embedded system is tightly coupled with heterogeneous layers such as application, as kernel, device driver, HAL and hardware. Embedded system is customized for the specific purpose and hardware. In addition, the product cycle is so fast that software and hardware, which are developed by several vendors, are integrated together under unstable status. Therefore, there are lots of possibilities of faults in all layers. Because embedded software developers test their codes integrated with faulty layers, they cannot confirm 'whether testing of every aspects was completed, their code was failed, or integrated software/hardware has some problems'. In this paper, we propose an embedded software interface test method and a test tool called Justitia for detecting faults and tracing causes in the interface among heterogeneous layers. The proposed technique is an automated method which improves debugging upto professional testing using an emulator for helping developer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.100-103
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• 2008

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800k gate counts using Charterd 0.18um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.112-115
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• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• Transactions of the Korean Society of Automotive Engineers
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• v.9 no.6
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• pp.186-194
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• 2001

To meet the challenge of testing increasingly complex automotive control systems, the real-time hardware-in-the-loop(HIL) simulation technology has been developed. In this paper, a strategy for evaluation of semiactive suspension systems using real-time HIL simulation is presented. A multibody vehicle model is adopted to simulate vehicle dynamic motions accurately. Accuracy of the vehicle simulation results is compared to that of the real vehicle field test and proven to be very accurate. The controller and stepping motor to adjust semi-active damper stage are equipped as external hardwares and connected to the real-time computer which has vehicle dynamic model. Open and closed loop test methods are used to evaluate a controlled suspension system and the system's operations are verified it is found that the proposed evaluation methods can be used well for the verification of semi-active suspension systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2647-2654
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• 2009

In this paper, we propose H.264 Encoder integrating Intra Prediction, Deblocking Filter, Context-Based Adaptive Variable Length Coding, and Motion Estimation encoder module. This designed module can be operated in 440 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 9.4 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 166MHz clock system, and has 1800K gate counts using Charterd 0.18 um process including SRAM memory. Manufactured chip has the size of $6{\times}6mm$ and 208 pins package.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2045-2049
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• 2008

In this paper, we propose an novel architecture for H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18 um process including SRAM memory.

• Journal of Advanced Navigation Technology
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• v.25 no.5
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• pp.377-383
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• 2021

In this paper, we describe the case of automatic test equipment development for hardware verification of stores management computer mounted on aircraft. Recently, the required functions of aircraft have been diversified and the related technologies of avionics equipment have developed, and the types and quantity of interfaces required for avionics equipment have increased. In addition to the existing old stores, the stores management computer also needs to control the interface in large quantities as the requirements for the new stores are added. For this reason, the time and manpower required for the inspection of avionic equipment are also increasing, and if the test process of avionic equipment can be automated and unmanned, more efficient inspection system operation will be possible. Therefore, this paper introduces the case of designing test software and test scenario to automate the structural design contents and verification process of test equipment required for the verification of hardware function of stores management computer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.803-806
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• 2007

Since the different characteristics from the PRNG (Pseudo Random Number Generator) or various deterministic devices such as arithmetic processing units, new concepts and test methods should be suggested in order to test TRNG (Ture Random Number Generator). Deterministic devices can be covered by ATPG (Automatic Test Pattern Generation), which uses patterns generated by cyclic shift registers due to its hardware oriented characteristics, pure random numbers are not possibly tested by automatic test pattern generation due to its analog-oriented characteristics. In this paper, we studied and analyzed a hardware/software combined test method named Diehard test, in which we apply continuous pattern variation to check the statistics. We also point out the considerations when making random number tests.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.10-21
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• 1998

In this paper, we analyze the problems of conventional and previous mehtod on delay test method in IEEE 1149.1. To solve them, we propose two kinds of delay test architectures. One is called ARCH-C, is for combinatonal circuit, and the other is ARCH-S, for clocked sequential circuit. ARCH-C is able to detect delay defect of 0.5 $T_{tck}$ or 1 $T_{tck}$ size. And ARCH-C have a fixed and small amount of hardware overhead, on the contrary preious method has a hardware overhead on the dependent of CUT. This paper discusses weveral problems of Delay test on IEEE 1149.1 for clocked sequential circuit. We suggest the method called ARCH-S, is based on a clock counting technique to generate continuous clocked input of CUT. the simulation results ascertain the accurate operation and effectiveness of the proposed architectures.res.