• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.317-319
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• 2003

HILS(Hardware In-the Loop Simulation) is commonly used in the development and testing of embedded systems, when those systems cannot be tested easily, thoroughly, and repeated in their operational environments. HILS can be a useful tool to develop products more quickly and cost effectively and also reduces the possibility of serious defects being discovered after production. During the product development period, Design optimization and hardware/software debugging can be performed using HILS skill. This paper describes a HILS model for the STG(Steam-Turbine Generator) Simulator to prove the performance of the developed Digital Governor. It is developed using software technics which can confirm the responses of a real-time system.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• ETRI Journal
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• v.31 no.6
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• pp.732-740
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• 2009

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 ${\mu}m$ CMOS process and evaluated successfully on a real-time test board.

• Journal of Astronomy and Space Sciences
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• v.35 no.4
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• pp.263-277
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• 2018

This paper presents a vision-based relative pose estimation algorithm and its validation through both numerical and hardware experiments. The algorithm and the hardware system were simultaneously designed considering actual experimental conditions. Two estimation techniques were utilized to estimate relative pose; one was a nonlinear least square method for initial estimation, and the other was an extended Kalman Filter for subsequent on-line estimation. A measurement model of the vision sensor and equations of motion including nonlinear perturbations were utilized in the estimation process. Numerical simulations were performed and analyzed for both the autonomous docking and formation flying scenarios. A configuration of LED-based beacons was designed to avoid measurement singularity, and its structural information was implemented in the estimation algorithm. The proposed algorithm was verified again in the experimental environment by using the Autonomous Spacecraft Test Environment for Rendezvous In proXimity (ASTERIX) facility. Additionally, a laser distance meter was added to the estimation algorithm to improve the relative position estimation accuracy. Throughout this study, the performance required for autonomous docking could be presented by confirming the change in estimation accuracy with respect to the level of measurement error. In addition, hardware experiments confirmed the effectiveness of the suggested algorithm and its applicability to actual tasks in the real world.

• Publications of The Korean Astronomical Society
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• v.31 no.2
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• pp.11-19
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• 2016

This paper presents the results of test observations toward a point source, 4C39.25, for observation modes with various bandwidths and numbers of IF streams in order to examine a reliability of the Daejeon hardware correlator performance for correlating VLBI (Very Long Baseline Interferometry) data obtained with the several observation modes of the KVN (Korean VLBI Network). We used a DiFX software correlator (DiFX) as a reference, for investigating the output visibilities from the Daejeon corelator. It is found that the band shapes of the output visibilities from two correlators are similar to each other and the correlated flux density for each baseline obtained from the Daejeon hardware correlator is lower by 3 - 7% than that from the DiFX. The flux difference is attributed to the limitation of FPGA resources and the difference of fringe rotation algorithm of the Daejeon hardware correlator. The conversion factor, 0.93 ~ 0.97, is proposed for future correlation with the Daejeon hardware correlator.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.402-404
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• 1997

The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implements the ray tracing with software and hardware. Specially we designs the hit-test unit with FPGA tool for the ray-tracing.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.5
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• pp.623-629
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• 2018

The acceleration and the angular velocity that include natural frequencies of a missile detected by Inertial Measurement Unit(IMU) are transmitted to the control loop of a missile. The control loop command that is calculated using above signals can cause the resonance of the missile while it flies. Hence it is common to adapt the filter and the control loop for attenuating or eliminating the undesired signals such as natural frequencies. This paper introduces the new test technique using a floating system for performance evaluation of the designed filter and the control loop prior to a flight test. The proposed scheme can check out the degradation property of vibration in the filter and the control loop, while the conventional hardware-in-the-loop simulation(HILS) scheme cannot.

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2298-2306
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• 2017

A PMS (Power Management System) controls vessel's power systems to improve the system efficiency and to protect a blackout condition. The PMS should be developed with considering the type and the capacity of the vessel's power system. It is necessary to test the PMS functions developed for vessel's safe operations under various sailing situations. Therefore, the function tests in cooperation with practical power systems are required in the PMS development. In this paper, a hardware-in-the-loop (HIL) simulator is developed for the purposes of the PMS function tests. The HIL simulator can be more cost-effective, more time-saved, easier to reproduce, and safer beyond the normal operating range than conventional off-line simulators, especially at early stages in development processes or during fault tests. Vessel's power system model is developed by using a MATLAB/SIMULINK software and by communicating between an OPAL-RT's OP5600 simulator. The PMS uses a Modbus communication protocol implemented using LabVIEW software. Representative tests of the PMS functions are performed to verify the validity of the proposed HIL-based test platform.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.10
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• pp.898-906
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• 2002

Antilock Brake System (ABS) is designed to prevent wheels from being locked-up under emergency braking of a vehicle. Therefore it improves directional stability of the vehicle, shortens stopping distance, and enhances maneuvering during braking, regardless of road conditions. Hardware In-the-Loop Simulation (HILS) is an effective tool for design Performance evaluation and test of vehicle subsystems such as ABS, active suspension, and steering systems. This paper describes a HILS model for ABS/ ASR(Acceleration Slip Regulation) system applications. A fourteen degrees-of-freedom vehicle dynamics model is simulated in an alpha-chip processor board. The proposed HILS system is tested with a basic ABS control algorithm. The design and implementation of HILS system for the ABS ECU(Electronic Control Unit) development of commercial vehicle are presented. The results show that the proposed HILS system can be used to test the performance, stability, and reliability of a vehicle under braking.