• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.11a
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• pp.241-243
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• 2020

The high computational complexity of deep learning algorithms has led to the development of specialized hardware architectures. However, soft errors (bit flip) may occur in these hardware systems due to voltage variation and high energy particles. Many error correction methods have been proposed to counter this problem. In this work, we analyze an error correction mechanism based on repetition codes and an activation function. We test this method by injecting errors into weight filters and define an ideal error rate range in which the proposed method complements the accuracy of the model in the presence of error.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.898-905
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• 2018

In this work, infrared targets for a developed hardware-in-the-loop simulation(HILS) system are proposed for a performance test of a dual-sensor imaging seeker equipped with an infrared and a visible sensor that can lock and track for ground and air targets. This integrated system is composed of 100 modules of heat and light sources to simulate various kinds of target and the trajectory of moving targets based on scenarios. It is possible to simulate not only the position, velocity, and direction for these targets but also background clutter and jamming environments. The design and measurement results of an infrared target, such as the HILS system configuration, developed for testing and evaluation of a dual-sensor imaging seeker are described. In the future, it is planned to test the lock-on and tracking performance of an imaging seeker equipped with single or dual sensors dynamically in real time based on a simulation flight scenario in the developed HILS system.

• Journal of the Institute of Convergence Signal Processing
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• v.17 no.2
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• pp.53-60
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• 2016

In this paper, we introduce the implementation and test results of a new method of correlated result storage to achieve the full performance of the Daejeon hardware correlator. Recently, the observation of 8 Gbps speed, which is the maximum observational standard of KVN(Korean VLBI Network), has been performed. The correlation processing using the Daejeon hardware correlator is also required. Therefore, a new correlation result storage introduction has become necessary. The maximum correlation result output speed of the Daejeon hardware correlator is 1.4 GB/sec per 25.6 ms integration time. The conventional correlation result storage system can not cope with the maximum correlation output speed of the Daejeon hardware correlator, and the output speed is limited to 1/4. That is, among the four input ports of the Daejeon hardware correlator, the three inputs are limited to correspond to the observation rate of 1 Gbps. This new storage system uses the Gluster file system among many of the latest technologies used in storage systems. In tests that meet the maximum output rate of 1.4 GB/sec for the Daejeon hardware correlator, 350 MB/sec for each of the four optical outputs, resulting in 1.4 GB/sec in total.

• ETRI Journal
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• v.33 no.1
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• pp.140-143
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• 2011

Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.227-227
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• 2004

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.47.2-47
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• 2002

$\textbullet$ Introduction of aviation navigation $\textbullet$ Integrated navigation algorithm $\textbullet$ Description of hardware system $\textbullet$ Ground test $\textbullet$ Flight test $\textbullet$ Conclusion

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.594-597
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• 2005

This paper shows that the defect detection in TFTarray panel can be improved by using newly developed software solution without adding additional hardware instruments. Some issues are reviewed in current TFT array test and new algorithm is explained for detecting more real defects without paying the penalty of reporting more false defects in TFT array test.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.110-115
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• 2014

The reconfigurability of FPGA devices allows designers to evaluate, test and validate a new control algorithm; a new component or prototypes without damaged the real system with the so-called hardware co-simulation. The present paper uses the Xilinx System Generator (XSG) environment to establish and validate a new nonlinear estimator for the rotor time constant inverse that will be exploited to improve the indirect rotor field control of induction motor.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.2
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• pp.155-167
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• 1998

The prevalence of microprocessor-based controllers in automotive systems has greatly increased the meed for tools which can be used to validate and test control systems over their full range of operation. The objective of this paper is to develop a real time simulator of an anti-lock braking system and the methodology of using hardware-in-the-loop simulation based on a personal computer. By use of this simulator, the analyses of a commercial electronic control unit as well as the validation of the developed control logics for ABS were performed successfully. The simulator of this research can be traction applied to development of more advanced control system, such as traction control systems, vehicle dynamic control system and so forth.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.5
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• pp.222-227
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• 1998

Collision warning systems have been an active research and development area as the interests and demands for ASV's (Advanced Safety Vehicles) have increased. This paper presents an experimental investigation of a collision warning system for automobiles. A collision warning HiLS(Hardware-in-the-Loop Simulation) system has been designed and used to test the collision warning algorithm, radar sensors, and warning displays under realistic operating conditions in the laboratory. the collision warning algorithm is operated by a warning index, which is a function of the warning distance and the braking distance. The computer calculates velocities of the preceding vehicle and following vehicle, relative distance and relative velocity of the vehicles using vehicle simulation models. The relative distance and the relative velocity are applied to the vehicle simulator controlled by a DC motor.