• 제목/요약/키워드: Hardware sharing

검색결과 171건 처리시간 0.024초

블록암호와 해시함수의 통합 보안 프로세서 구현 (An Unified Security Processor Implementation of Block Ciphers and Hash Function)

  • 김기쁨;신경욱
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2017년도 추계학술대회
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    • pp.250-252
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    • 2017
  • 블록암호 국제표준 AES(Advanced Encryption Standard), 국내표준 ARIA(Academy, Research Institute, Agency) 및 국제표준 해시함수 Whirlpool을 통합 하드웨어로 구현하였다. ARIA 블록암호와 Whirlpool 해시함수는 AES와 유사한 구조를 가지며, 본 논문에서는 저면적 구현을 위해서 하드웨어 자원을 공유하여 설계하였다. Verilog-HDL로 설계된 ARIA-AES-Whirlpool 통합 보안 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였고, $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 20 MHz의 동작 주파수에서 71,872 GE로 구현되었다.

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Single Address Space(SAS) Architecture를 이용한 Embedded Operating System (Embedded Operating System using the Single Address Space(SAS) Architecture)

  • 안광혁
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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    • pp.608-611
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    • 2003
  • A large part of the embedded system, compared with the PC, have low performance CPU and small memory. So the embedded operating system fits the condition of that hardware system. A Single Address Space (SAS) OS has the operating system and all applications in the single address space. The SAS architecture enhances sharing and co-operation, because addresses have a unique interpretation. Thus, pointer-based date structures can be directly communicated and shared between programs at any time, and can be stored directly on storage. The key point of the SAS OS on the embedded system is the low overhead inter-action between programs in process and usage. So SAS OS can be ported on the low performance CPU. In this paper, we design the SAS OS (named emNOS, Embedded Network Operating System) on the ARMTTDMI processor. Finally we show the benefits of the SAS OS on the embedded system.

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화소-병렬 영상처리를 위한 포맷 변환기 설계 (Design of Format Converter for Pixel-Parallel Image Processing)

  • 김현기;이천희
    • 한국시뮬레이션학회논문지
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    • 제10권3호
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    • pp.59-70
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    • 2001
  • Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

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오픈 소스를 활용한 소형 드론 설계와 제작에 대한 연구 (A Design of Small Drone with Open Source Frame and Software)

  • 이준하
    • 반도체디스플레이기술학회지
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    • 제18권2호
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    • pp.78-81
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    • 2019
  • In this study, we will analyze the design, development and application of these small drones using open source. These drones are used in flight exercises, aerial photography, and coding education. In the era of the fourth industrial revolution, such as the development of sensor technology, expansion of open source sharing, and application of artificial intelligence, Is expected to be able to demonstrate convergence. In this paper, we have studied the design and fabrication of small drones using open source. In the case of drones, various functions and differentiated materials are required depending on the application, and the future development of the unmanned mobile object, namely the drone, in which the creativity and the technology are combined with each other continues to be enhanced by the improvement of autonomy and artificial intelligence. Software-based architecture-based technologies have been developed in collaboration with embedded SWs that combine sensors, motors, and control systems. In hardware, it is customary to use a combination of materials and design to increase the freedom of design. It will be made in a free structure.

스마트 기기 간의 정보 공유를 위한 복합 환경센서 플랫폼 설계 (Design of an Compound Environment Sensing Platform for Sharing Environment Information between Smart Devices)

  • 송병철;임승옥;서정욱
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2014년도 추계학술대회
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    • pp.543-544
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    • 2014
  • 본 논문에서는 스마트 기기(게이트웨이, 폰, 패드 등)와 정보를 공유하기 위한 복합 환경센서 플랫폼을 설계한다. 복합 환경센서 플랫폼은 온/습도 센서, 토양 온도/습도 센서, 태양광 센서 등을 하나의 플랫폼에서 지원할 수 있도록 설계되었으며, 수집된 정보는 ZigBee 통신을 통해 스마트 게이트웨이로 전달되고, 이 게이트웨이를 통해 스마트 폰/패드 등과 트윗트를 통해 정보를 공유할 수 있다.

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ARIA-AES 블록암호의 효율적인 구현 (An Efficient Implementation of ARIA-AES Block Cipher)

  • 김기쁨;신경욱
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2016년도 추계학술대회
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    • pp.155-157
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    • 2016
  • 한국 표준 블록암호 알고리듬 ARIA(Academy, Research Institute, Agency)와 미국 표준인 AES(Advanced Encryption Standard) 알고리듬은 128-비트 블록 길이를 지원하고 SPN(substitution permutation network) 구조를 특징으로 가져 서로 유사한 형태를 지닌다. 본 논문에서는 ARIA와 AES를 선택적으로 수행하는 ARIA-AES 통합 프로세서를 효율적으로 구현하였다. Verilog HDL로 설계된 ARIA-AES 통합 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였고, $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 100KHz의 동작주파수에서 합성한 결과 39,498 GE로 구현되었다.

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클라우드-IP 기반의 방송 미디어 제작 기술 동향 (Cloud-IP based Broadcasting Media Production Technology)

  • 오혜주;이재영;김순철;최동준
    • 전자통신동향분석
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    • 제37권6호
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    • pp.64-73
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    • 2022
  • This document describes the technologies related to internet protocol (IP)-based media production systems. As high-capacity, high-quality data transmission increases, broadcast production platforms are shifting to IP. The IP-based production system uses the network by sharing resources and is easy to control centrally. It also facilitates software-based cloud production. A cloud IP-based media production platform can work regardless of dedicated hardware and can easily collaborate. Associations and industrial groups have created common standards related to production, and manufacturers are developing solutions with their technologies based on their product competitiveness. This study investigates the open standard technologies used for IP-based media production and technology trends in the ProAV industry and describes the production in the cloud environment and cloud AI-based production technology trends.

Research on the Application of Gamification in Fitness App Based on Kano Model

  • Jing Ren;Chang-wook Lee
    • International Journal of Internet, Broadcasting and Communication
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    • 제16권2호
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    • pp.136-148
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    • 2024
  • In recent years, public attention to health and wellness issues has increased. The integration of smart fitness hardware and innovative technologies have made the development of smart fitness a trend. The number of fitness applications in the market has surged, and demand for an optimal experience is increasingly high. This study selects Sweatcoin, Home Workout, Six Pack in 30 Days, and Fitness Coach & Diet as research subjects from the top ten global mobile health and fitness apps in 2022 based on download rankings. The research is based on eight gamification elements: motivation, challenge, achievement, relationships, sharing, reward, level, and competition, identified through preliminary studies. We distributed a total of 166 questionnaires to users and collected 163 valid responses for data analysis. The Kano Model was used to study the desires of fitness enthusiasts using fitness apps. To reduce the limitations of the research results, the Better-Worse Method was employed for satisfaction index analysis. Based on the final analysis, we propose suggestions for improvement for the four fitness apps to better meet user needs and create a more attractive and efficient application experience.

사물-사람 간 개인화된 상호작용을 위한 음향신호 이벤트 감지 및 Matlab/Simulink 연동환경 (Acoustic Event Detection and Matlab/Simulink Interoperation for Individualized Things-Human Interaction)

  • 이상현;김탁곤;조정훈;박대진
    • 대한임베디드공학회논문지
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    • 제10권4호
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    • pp.189-198
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    • 2015
  • Most IoT-related approaches have tried to establish the relation by connecting the network between things. The proposed research will present how the pervasive interaction of eco-system formed by touching the objects between humans and things can be recognized on purpose. By collecting and sharing the detected patterns among all kinds of things, we can construct the environment which enables individualized interactions of different objects. To perform the aforementioned, we are going to utilize technical procedures such as event-driven signal processing, pattern matching for signal recognition, and hardware in the loop simulation. We will also aim to implement the prototype of sensor processor based on Arduino MCU, which can be integrated with system using Arduino-Matlab/Simulink hybrid-interoperation environment. In the experiment, we use piezo transducer to detect the vibration or vibrates the surface using acoustic wave, which has specific frequency spectrum and individualized signal shape in terms of time axis. The signal distortion in time and frequency domain is recorded into memory tracer within sensor processor to extract the meaningful pattern by comparing the stored with lookup table(LUT). In this paper, we will contribute the initial prototypes for the acoustic touch processor by using off-the-shelf MCU and the integrated framework based on Matlab/Simulink model to provide the individualization of the touch-sensing for the user on purpose.

H.264용 디블로킹 필터의 저전력 구조 (Low-power Structure for H.264 Deblocking Filter)

  • 장영범;오세만;박진수;한규훈;김수홍
    • 대한전자공학회논문지SP
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    • 제43권3호
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    • pp.92-99
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    • 2006
  • 이 논문에서는 H.264 비디오 코딩에 사용되는 디블로킹 필터의 저전력 구조를 제안하였다. 즉, 8 픽셀의 입력에 대한 공통의 필터계수를 공유함으로써 구현 하드웨어를 줄일 수 있는 효율적인 구조를 제안하였다. 제안된 디블로킹 필터 구조는 MUX와 DEMUX 회로를 추가하여 설계하였으며, 기존 구조와 비교하여 44.2%의 덧셈연산 감소효과를 나타내었다. 또한 제안된 구조를 Verilog HDL 코딩과 FPGA로 구현한 결과, 기존의 디블로킹 필터 구조와 비교하여 각각 19.5%와 19.4%의 게이트 카운트 감소 효과를 보였다. 따라서 제안된 디블로킹 필터 구조는 H.264용 encoder와 decoder SoC에 널리 사용될 수 있는 저전력 구조이다.