• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.289-294
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• 1986

In this paper, we describe the development of an NIU (network interface unit) hardware for sharing computer resources and exchanging haigh-speed information between information systems distributed in a local area. The NIU designed and implemented in accordance with Ethernet specifications is operating normally with the upper layer software. Modular design makes it simple to change or expand the functions of the NIU. The NIU's are connected to 10Mbps coaxial cable through transceivers. In addition, a system and a design specifications for the NIU of a broadband LAN based on the K-LAN NIU are porposed.

• The Journal of Asian Finance, Economics and Business
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• v.6 no.2
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• pp.203-212
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• 2019

A system Integrator (SI) makes a consortium with multiple providers of hardware and software solutions to sell an information system. The success of information systems (IS) mainly depends on establishing a trustful relationship between SI supplier and client, and delivering high-quality system. However, the determinants of trust and system quality have been investigated mostly from the perspective of s ystem buyers rather than system sellers. This study examines the influence of key variables that SI can handle to improve trust and system quality which finally leads to user satisfaction toward SI. This study adopts resource complementarity, user participation and information sharing as the key variable then builds a research model to explain their relationships to user satisfaction. Respondents are recruited from 251 firms that have built any information system in recent two years in South Korea. Results of partial least square (PLS) modeling analysis show that both resource complementarity and information sharing have positive relationships with trust. Also the relationships between trust, system quality and user satisfaction toward S.I are supported. In addition, the mediating roles of trust and system quality are identified. We discussed some of the key managerial and theoretical implications of the paper and suggested further research directions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.91-94
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• 2012

This paper describes an efficient implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit specified in the standard. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 33,218 gates and the estimated throughput is about 640 Mbps at 100 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.1-9
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• 2010

In this paper, the novel architecture of Intra-prediction & DCTQ hardware, which can process for the Full HD image($1980{\times}1088$@30fps) in realtime, is proposed. The cycle optimization method for the overall cycle of prediction, transform, scaling, descaling, and reconstruction is proposed. To reduce the cycle in the $4{\times}4$ prediction, the quantization process is performed during the prediction cycle and pre-selection of 2 modes among the 9 modes is performed to reduce the hardware area. To reduce the hardware of $16{\times}16$ and $8{\times}8$ prediction, the sharing logic between 2 prediction is utilized. The proposed architecture can process the 30frame/sec of full HD image in 108 MHz clock and operate 425 cycle for one macroblock.

• Journal of KIISE
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• v.42 no.2
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• pp.177-182
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• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.20 no.44
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• pp.475-483
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• 1997

Industrial safety management program consists of three part which is education, technology and control. The effectiveness of industrial safety control program rely on the ability of controlling hardware system, technology and software, training and management. How to design and develop the sharing machine fault and safety diagnosis system using expert system technique is presented on this paper.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1217-1220
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• 2003

A low-power design technique for lithium-ion Battery-Protection Integrated Circuit (BPIC) for multi cell configuration is proposed. The hardware sharing scheme with more precisely divided operating states in the detection range could reduce the power consumption significantly, especially during the normal state. The usefulness of the proposed scheme was confirmed through HSPICE simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.503-512
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• 2001

The general DSP algorithm, like orthogonal transform or filter processing, needs efficient hardware architecture to compute inner product. The typical MAC architecture has high cost of silicon. Because of this reason, the distributed arithmetic without multiplier is widely used for implementing inner product. This paper presents the optimization to reduce required hardware in distributed arithmetic by using extraction method of adder sharing component. The optimization process uses Boltzmann-machine which is one of the neural network. This proposed method can solve problem that is increasing complexity depending on depth of inner product and compose optimal summation-network with the minimum FA and FF in a few time. The designed DCT by using Proposed method is more efficient than a ROM-based distributed arithmetic.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.949-955
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• 2018

Hardware-in-the-loop (HIL) simulation is a technique that can be employed for developing and testing complex real-time embedded systems. HIL simulation provides an effective platform for verifying power management system (PMS) performance of liquefied natural gas carriers, which are high value-added vessels such as offshore plants. However, HIL tests conducted by research institutes, including domestic shipyards, can be protracted. To address the said issue, this study proposes a field programmable gate array (FPGA) based PMS-HIL simulator that comprises a power supply, consumer, control console, and main switchboard. The proposed HIL simulation platform incorporated actual equipment data while conducting load sharing PMS tests. The proposed system was verified through symmetric, asymmetric, and fixed load sharing tests. The proposed system can thus potentially replace the standard factory acceptance tests. Furthermore, the proposed simulator can be helpful in developing additional systems for vessel automation and autonomous operation, including the development of energy management systems.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.445-454
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• 2006

Almost of industrial measuring instruments usually are equipped only with serial communication devices. In order to connect these instruments to internet, we implement an embedded translator. This device has the hardware components composed of one WAN port, two LAN ports, and two UARTs, and functions as a communication translator between serial and internet communication. it also provides web-based monitoring function that is absent from existing serial-to-ethernet converter. The hardware is implemented using the KS8695 network processor which s an ARM922T as processor core. We have installed the boa web server and utilized the CGI function for internet-based remote control, added the IP sharing function which allows the network with private IP addresses to access the internet, and developed a serial-to-ethernet translation program. Finally, we show an application example of the developed translator that remotely monitors the solar energy production system.