• Journal of Broadcast Engineering
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• v.25 no.6
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• pp.965-972
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• 2020

Depth maps have distance information of objects. They play an important role in organizing 3D information. Color and depth images are often simultaneously obtained. However, depth images have lower resolution than color images due to limitation in hardware technology. Therefore, it is useful to upsample depth maps to have the same resolution as color images. In this paper, we propose a novel method to upsample depth map by shifting the pixel position instead of compensating pixel value. This approach moves the position of the pixel around the edge to the center of the edge, and this process is carried out in several steps to restore blurred depth map. The experimental results show that the proposed method improves both quantitative and visual quality compared to the existing methods.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.2
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• pp.189-200
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• 2012

With increasing the number of smart device such as Tablet PC, smart phone and netbook, information security which based on smart device in mobile environment have become the issue. It is important to enter a password safety. In various types of mobile devices, because of hardware limitation of device, it is difficult that to equip secondary input device such as keyboard and mouse. Also, a loss of accuracy becomes a problem because input information was entered by touch screen. Because of problem mentioned above it can be predicted to change password scheme text based password scheme to graphical password scheme, graphical password scheme is easy to use and is resistant to shoulder surfing attack. So this paper proposes new graphical password scheme based 5 strokes which are made by decomposed the Korean to defend against shoulder surfing attack.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.6
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• pp.1075-1080
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• 2020

The development of computing technology and networking is developing as the fundamental technology of the 4th industrial revolution. AR and VR technologies, which are dual realistic media fields, are developing into many application areas, especially! The potential for development in the medical field is very high. As for the development potential of the health care field, the 4th industrial revolution such as AR/VR to solve problems, such as the increase of various chronic diseases due to the aging of the population, the limitation of infrastructure that can deal with them, and the lack of specialized personnel. It is adopting services in the healthcare field using representative technologies. Accordingly, AR/VR in the healthcare field occupies about 17% of the total industrial market. Therefore, in this study, cognitive judgment technology using AR applies cognitive evaluation through a computing system to the mild cognitive impairment, and based on the results, researches to utilize cognitive rehabilitation contents using augmented reality, and hardware necessary for cognitive judgment technology. Also, software design to help in the field of cognitive judgment technology and healthcare using AR.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.331-339
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• 2017

This paper proposes a thread pool management technique of an websocket server that is applicable to embedded systems. WebSocket is a proposed technique for consisting a dynamic web, and is constructed using HTML5 and jQuery. Various studies have been progressing to construct a dynamic web by Apache, Oracle and etc. Previous web service systems require high-capacity, high-performance hardware specifications and are not suitable for embedded systems. The node.js which is consist of HTML5 and jQuery is a typical websocket server which is made by open sources, and is a java script based web application which is composed of a single thread. The node.js has a limitation on the performance for processing a high velocity data on the embedded system. We make up a multi-thread based websoket server which can solve the mentioned problem. The thread pool is managed by a bit register and suitable for embedded systems. To evaluate the performance of the proposed algorithm, we uses JMeter that is a network test tool.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

• Journal of Practical Engineering Education
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• v.5 no.2
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• pp.101-107
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• 2013

Clickers that are personal response systems are a technology used to promote active learning and most research on the benefits of using clickers has shown that students become engaged and enjoy using them. But, existing clickers consisting of hardware devices and aggregation software provide simple response and aggregation function and it costs a lot. In this paper, in order to resolve the limitation of the existing clickers, we've designed and implemented the Smart Clicker consisting of a smartphone application for students and a web application & a MFC program for professors. Students can answer professor's questions with O/X or numbers or text and even ask questions with text messaging by using Smart Clicker in the classroom. Professors can see students' answers or questions immediately and check up students' response participation rate on the web page. Besides, the Smart Clicker will help professors actively engage students during the entire class period and gauge their level of understanding of the material being presented, and provide prompt feedback to student questions. As a result, we expect that quality of education will be increased.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.6
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• pp.467-478
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• 2020

Hypervisor virtualize hardware resources to utilize them more effectively. At the same time, hypervisor's characteristics of time and space partitioning improves reliability of flight software by reducing a complexity of the flight software. Korea Aerospace Research Institute chooses one of hypervisors for space, XtratuM, and examine its applicability to the flight software. XtratuM has strong points in performance improvement with high reliability. However, it does not support SMP. Therefore, it has limitation in using it with high performance applications including satellite altitude orbit control systems. This paper proposes RTEMS XM-SMP to support SMP with RTEMS, one of real time operating systems for space. Several components are added as hypercalls, and initialization processes are modified to use several processors with inter processors communication routines. In addition, all components related to processors are updated including context switch and interrupts. The effectiveness of the developed RTEMS XM-SMP is demonstrated with a GR740 board by executing SMP benchmark functions. Performance improvements are reviewed to check the effectiveness of SMP operations.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.66-75
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• 2016

Due to aggressive scaling of device sizes and reduced noise margins, physical defects caused by aging and process variation are continuously increasing. Additionally, with scaling limitation of metal wire and the increasing of communication volume, fault tolerant method in manycore network-on-chip (NoC) has been actively researched. However, there are few researches investigating reliability in NoC with voltage-frequency-island (VFI) regime. In this paper, we propose a table-based routing technique that can communicate, even if link failures occur in the VFI NoC. The output port is alternatively selected between best and the detour routing path in order to improve reliability with minimized hardware cost. Experimental results show that the proposed method achieves full coverage within 1% faulty links. Compared to $d^2$-LBDR that also considers a routing method for searching a detour path in real time, the proposed method, on average, produces 0.8% savings in execution time and 15.9% savings in energy consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.62-71
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• 2001

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.10
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• pp.89-100
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• 2007

Consumer Portal is defined as "a combination of hardware and software that enables two-way communication between energy service provider(ESP, like KEPCO) and equipment within the consumer's premises". The portal provides both a physical link(between wires, radio waves, and other media) and a logical link(translating among language-like codes and etiquette-like protocols) between in-building and wide-area access networks. Thus, the consumer portal is an important, open public shared infrastructure in the future vision of energy services. In this paper, we describe a new methodology for local communication and computer network capacity design of consumer portal, and also presents capacity calculation method using a network system limitation factors. By the approach, we can check into the limitations of existing methods, and propose an improved data processing algorithm that can expand the maximum number of the networked end-use devices up to $30{\sim}40$ times. For validation, we applies the proposed methode to our real system design. Our contribution will help electrical power information network design.