• Electronics and Telecommunications Trends
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• v.36 no.6
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• pp.78-87
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• 2021

Information technology (IT) has been applied to various fields, and currently, IT devices and systems are used in very important areas, such as aviation, industry, and national defense. Such devices and systems are subject to various types of malicious attacks, which can be software or hardware based. Compared to software-based attacks, hardware-based attacks are known to be much more difficult to detect. A hardware Trojan horse is a representative example of hardware-based attacks. A hardware Trojan horse attack inserts a circuit into an IC chip. The inserted circuit performs malicious actions, such as causing a system malfunction or leaking important information. This has increased the potential for attack in the current supply chain environment, which is jointly developed by various companies. In this paper, we discuss the future direction of research by introducing attack cases, the characteristics of hardware Trojan horses, and countermeasure trends.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.740-743
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• 2015

The increasing complexity of integrated circuits and IP-based hardware designs have created the risk of hardware Trojans. This paper introduces a new type of threat, the coherence-exploiting hardware Trojan. This Trojan can be maliciously implanted in master components in a system, and continuously injects memory read transactions on to bus or main interconnect. The injected traffic forces the eviction of cache lines, taking advantage of cache coherence protocols. This type of Trojans insidiously slows down the system performance, incurring Denial-of-Service (DoS) attack. We used Xilinx Zynq-7000 device to implement and evaluate the coherence-exploiting Trojan. The malicious traffic was injected through the AXI ACP interface in Zynq-7000. Then, we collected the L2 cache eviction statistics with performance counters. The experiment results reveal the severe threats of the Trojan to the system performance.

• Journal of Internet Computing and Services
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• v.21 no.2
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• pp.109-119
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• 2020

The FPGAs are semiconductors that can be redesigned after initial fabrication. It is used in various embedded systems such as signal processing, automotive industry, defense and military systems. However, as the complexity of hardware design increases and the design and manufacturing process globalizes, there is a growing concern about hardware trojan inserted into hardware. Many detection methods have been proposed to mitigate this threat. However, existing methods are mostly targeted at IC chips, therefore it is difficult to apply to FPGAs that have different components from IC chips, and there are few detection studies targeting FPGA chips. In this paper, we propose a method to detect hardware trojan by learning the static features of hardware trojan in LUT-level netlist of FPGA using machine learning.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.29-32
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• 2012

하드웨어 Trojan은 악의적인 목적으로 전자 회로망에 수정을 가한 회로로, Trojan 설계자의 목적에 따라 특정 환경에서 동작(Trigger) 되어 전체 시스템에 심각한 보안문제를 초래할 수 있다. 일반적으로 Trojan은 동작 시 시스템의 방화벽이나 보안 장치 등의 시스템 일부를 하드웨어적으로 무력화 시켜 제 기능을 상실시키며 심각한 경우 시스템 전반에 걸쳐 모든 기능을 마비시킬 가능성이 있다. 본 연구에서는 군사 시설과 같이 고도의 보안 및 정확성이 요구되는 시스템 분야에서 신뢰성 향상에 초점을 두고, 서로 다른 프로세서에서 같은 연산을 처리하여 이를 비교할 수 있는 Vote Counter를 탑재한 이질 시스템(Heterogeneous system)을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.24-26
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• 2013

Undefined Instruction 하드웨어 Trojan 은 정의되지 않은 명령어가 명령어 버스를 통해 CPU 에 유입될 경우 발현되어 CPU 의 전반적인 기능을 마비시킬 수 있는 하드웨어 Trojan 이다. 일반적으로 대부분의 상용화된 CPU 는 Undefined Instruction 에 대한 예외 처리를 지원하는데, ARM 의 경우 파이프 라인의 실행 단계에서 Undefined Instruction 임을 판별한다. 본 연구에서는 파이프 라인의 명령어 추출단계에서 발현되어서 명령어 해독단계에는 다른 명령어를 전달 시킴으로써 Undefined Instruction 예외처리를 피할 수 있는 하드웨어 Trojan 을 설계하고, 이를 방지하는 대응책을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.72-74
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• 2013

DoS(Denial of Service) 공격은 시스템을 악의적으로 공격해 해당 시스템의 자원을 부족하게 하여 원래 의도된 용도로 사용하지 못하게 하는 공격이다. 본 연구에서는 CPU의 인터럽트 처리 메커니즘을 악용한 하드웨어 Trojan의 DoS 공격 방법과 대응방안에 대해 연구한다. 이 연구에서 제안하는 하드웨어 Trojan은 기존 DoS 공격이 지속적인 서비스 요청으로 의도된 서비스가 불가능하게 하는 것과 유사하게 인터럽트를 지속적으로 발생시켜 CPU가 정상적인 동작을 할 수 없도록 한다. 본 연구에서는 이에 대한 대응 방법으로 인터럽트 서비스 루틴 코드의 수정을 통한 대응 및 Trojan 발견 방법에 대해서 제시한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.5
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• pp.1225-1231
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• 2018

FPGA-based system development is being developed as a form of outsourcing that shortens the development time and reduces the cost. Through the process, the risk of letting the hardware Trojan, which causes malfunctions, seep into the system also increases. Various detection methods are proposed for the issue; however, such type of hardware Trojans is inserted by modifying a bitstream directly and therefore, it is hard to detect with the suggested methods. To detect the type of hardware Trojans, it is essential to reverse-engineer the electric circuit implemented by bitstream to a distinguishable level. Specifically, it is important to reverse-engineer the routing information of the circuit that can identify the input-output flow of the signal. In this paper, we analyze the BIL bitstream reverse-engineering tool-chain that uses the algorithm, which retrieves the routing information from FPGA bitstream, and suggest the method to improve the tool-chain.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.343-350
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• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.