• Restorative Dentistry and Endodontics
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• v.20 no.2
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• pp.432-461
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• 1995

The basic principles in the design of Class II amalgam cavity preparations have been modified but not changed in essence over the last 90 years. The early essential principle was "extension for prevention". Most of the modifications have served to reduce the extent of preparation and, thus, increase the conservation of sound tooth structure. A more recent concept relating to conservative Class II cavity preparations involves elimination of occlusal preparation if no carious lesion exists in this area. To evaluate the ideal ClassII cavity preparation design, if carious lesion exists only in the interproximal area, three cavity design conditions were studied: Rodda's conventional cavity, simple proximal box cavity and proximal box cavity with retention grooves. In this study, MO amalgam cavity was prepared on maxillary first premolar. Three dimensional finite element models were made by serial photographic method. Linear, eight and six-nodal, isoparametric brick elements were used for the three dimensional finite element model. The periodontal ligament and alveolar bone surrounding the tooth were excluded in these models. Three types model(B option, Gap option and R option model) were developed. B option model was assumed perfect bonding between the restoration and cavty wall. Gap option model(Gap distance: $2{\mu}m$) was assumed the possibility of play at the interface simulated the lack of real bonding between the amalgam and cavity wall (enamel and dentin). R option model was assumed non-connection between the restoration and cavty wall. A load of 500N was applied vertically at the first node from the lingual slope of the buccal cusp tip. This study analysed the displacement, 1 and 2 direction normal stress and strain with FEM software ABAQUS Version 5.2 and hardware IRIS 4D/310 VGX Work-station. The results were as followed. 1. Rodda's cavity form model showed greater amount of displacement with other two models. 2. The stress and strain were increased on the distal marginal ridge and buccopulpal line angle in Rodda's cavity form model. 3. The stress and strain were increased on the central groove and a part of distal marginal ridge in simple proximal box model and proximal box model with retention grooves. 4. With Gap option, Rodda's cavity form model showed the greatest amount of the stress on distal marginal ridge followed by proximal box model with retention grooves and simple proximal box model in descending order. 5. With Gap option, simple proximal box model showed greater amount of stress on the central groove with proximal box model with retention grooves. 6. Retention grooves in the proximal box played the role of supporting the restorations opposing to loads.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.113-124
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• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.8
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• pp.547-565
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• 2009

Simulation is the imitation of some real thing, state of affairs, or process. The act of simulating something generally entails identifying certain key characteristics or behaviors of a selected physical or abstract system. And a simulator is the software or hardware tool that performs simulation tasks. When developing a simulator, the non-functional requirements such as modifiability, interoperability, and extendability should be required. However, existing studies about the simulator development focus not on such non-functional requirements but on the methodologies to build the simulation model. In this paper, we suggest the new architectural pattern for the software based simulator in consideration of such non-functional requirements. In order to define the architectural pattern, we identify the essential elements of the simulators, define relationships between them, and design the architectural structure with the elements to accommodate such non-functional requirements. According to the proposed pattern we can solve the simulation problems to combine the various simulation model components. The pattern guarantees modifiability by reconstructing the simulation model, also guarantees interoperability and extendability by adding various interfaces to the simulation model and by keeping the consistent interfacing mechanism between the simulation model components. The suggested architectural pattern can be used as the reference architecture of the simulator systems that will be developed in future.

• Korean Journal of Remote Sensing
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• v.26 no.2
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• pp.277-285
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• 2010

Geostationary Ocean Color Imager(GOCI-I), the world's first space-borne ocean color observation geostationary satellite, will be launched on June 2010. Development of GOCI-I took about 6 years, and its expected lifetime is about 7 years. The mission and user requirements of GOCI-II are required to be defined at this moment. Because baseline of the main mission of GOCI-II must be defined during the development time and early operational period of GOCI-I. The main difference between these missions is the global-monitoring capability of GOCI-II, which will meet the necessity of the monitoring and research on climate change in the long-term. The user requirements of GOCI-II will have higher spatial resolution, $250m{\times}250m$, and 12 spectral bands to fulfill GOCI-I's user request, which could not be implemented on GOCI-I for technical reasons. A dedicated panchromatic band will be added for the nighttime observation to obtain fishery information. GOCI-II will have a new capability, supporting user-definable observation requests such as clear sky area without clouds and special-event areas, etc. This will enable higher applicability of GOCI-II products. GOCI-II will perform observations 8 times daily, the same as GOCI-I's. Additionally, daily global observation once or twice daily is planned for GOCI-II. In this paper, we present an improved development and organization structure to solve the problems that have emerged so far. The hardware design of the GOCI-II will proceed in conjunction with domestic or foreign space agencies.

• Journal of the Korea Society of Computer and Information
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• v.15 no.9
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• pp.57-65
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• 2010

This paper describes the method of efficient container number recognition in colored container image with number plate at ATC(Automatic Transfer Crane) in container terminal yard. At the Sinseondae terminal gate in Busan, the container number recognition system is installed by "intelligent port-logistics system technology development", that is government research and development project. It is the method that it sets up the tunnel structure inside camera on the gate and it recognizes the container number in order to recognize the export container cargo automatically. However, as the automation equipment is introduced to the container terminal and the unmanned of a task is gradually accomplished, the container number recognition system for the confirmation of the object of work is required at ATC in container terminal yard. Therefore, the container number recognition system fitted for it is necessary for ATC in container terminal yard in which there are many intrusive of the character recognition through image including a sunlight, rain, snow, shadow, and etc. unlike the gate. In this paper, hardware components of the camera, illumination, and sensor lamp were altered and software elements of an algorithm were changed. that is, the difference of the brightness of the surrounding environment, and etc. were regulated for recognize a container number. Through this, a shadow problem, and etc. that it is thickly below hung with the sunlight or the cargo equipment were solved and the recognition time was shortened and the recognition rate was raised.

• Smart Media Journal
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• v.8 no.2
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• pp.29-38
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• 2019

With the advancement of information and communication technology, tactical networks are continuously being converted to All-IP future tactical networks that integrate all application services based on Internet protocol. Futuristic tactical mesh network is built with tactical WAN (wide area network) nodes that are inter-connected by a mesh structure. In order to guarantee QoS (quality of service) of application services, tactical service mesh (TSM) is suggested as an intermediate layer between infrastructure and application layers for futuristic tactical mesh network. The tactical service mesh requires dynamic QoS monitoring and control for intelligent QoS coordination. However, legacy networking nodes used for existing tactical networks are difficult to support these functionality due to inflexible monitoring support. In order to resolve such matter, we propose a tactical mesh WAN node as a hardware/software co-designed networking node in this paper. The tactical mesh WAN node is conceptually designed to have multi-access networking interfaces and virtualized networking switches by leveraging the DANOS whitebox server/switch. In addition, we explain how to apply eBPF-based traffic monitoring to the tactical mesh WAN node and verify the traffic monitoring feasibility for supporting QoS coordination of tactical-mesh traffic.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.2
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• pp.201-211
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• 2012

This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.1
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• pp.56-61
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• 2022

In this paper, we classify and present AI algorithms and natural language processing methods used in chatbots. A framework that can be used to implement a chatbot is also described. A chatbot is a system with a structure that interprets the input string by constructing the user interface in a conversational manner and selects an appropriate answer to the input string from the learned data and outputs it. However, training is required to generate an appropriate set of answers to a question and hardware with considerable computational power is required. Therefore, there is a limit to the practice of not only developing companies but also students learning AI development. Currently, chatbots are replacing the existing traditional tasks, and a practice course to understand and implement the system is required. RNN and Char-CNN are used to increase the accuracy of answering questions by learning unstructured data by applying technologies such as deep learning beyond the level of responding only to standardized data. In order to implement a chatbot, it is necessary to understand such a theory. In addition, the students presented examples of implementation of the entire system by utilizing the methods that can be used for coding education and the platform where existing developers and students can implement chatbots.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1172-1179
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• 2022

This paper describes a design of point scalar multiplier for public-key cryptography based on binary Edwards curves (BEdC). For efficient implementation of point addition (PA) and point doubling (PD) on BEdC, projective coordinate was adopted for finite field arithmetic, and computational performance was improved because only one inversion was involved in point scalar multiplication (PSM). By applying optimizations to hardware design, the storage and arithmetic steps for finite field arithmetic in PA and PD were reduced by approximately 40%. We designed two types of point scalar multipliers for BEdC, Type-I uses one 257-b×257-b binary multiplier and Type-II uses eight 32-b×32-b binary multipliers. Type-II design uses 65% less LUTs compared to Type-I, but it was evaluated that it took about 3.5 times the PSM computation time when operating with 240 MHz. Therefore, the BEdC crypto core of Type-I is suitable for applications requiring high-performance, and Type-II structure is suitable for applications with limited resources.