• Asia pacific journal of information systems
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• v.1 no.1
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• pp.5-16
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• 1991

Business firms have been expressing a strong interest in an effective structure of computing resources. In this respect previous studies provide some guidelines about the deployment of hardware, but the question of which information systems (IS) would be run under the dispersed hardware is still unanswered. The main purpose of the study is to analyze the relationship between various IS characteristics and the distribution of IS. The IS characteristics studied in this research include the usage frequency of IS in a dispersed plant, the currency of information required by the headquarter, the data volume processed in the plant, the relatedness of IS with other information systems in the plant. The survey was performed over the domestic, large manufacturing firms. The most noticeable finding is that the more the updated information is required in the headquarter, or the more related IS is to other information systems in the plant, the more IS is distributed.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.3-6
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• 2012

최근 응용 특화된 다양한 구조의 프로세서가 확산됨에 따라 기존 운영체제를 다른 구조의 플랫폼으로 이식하는 비용이 증가하고 있다. 기존 운영체제에서는 소스 코드 수준에서 하드웨어 의존적인 부분을 HAL(hardware abstraction layer)로 구분하여 관리함으로써 이기종 플랫폼간의 이식성을 높이고자 하였다. 그러나 기존 HAL 구조는 대부분 하드웨어의 물리적인 구조만을 고려하여 설계되어 체계적인 이식 작업이 어렵다는 문제점을 가지고 있다. 이를 위해 본 논문에서는 하드웨어의 물리적인 구조와 운영체제의 기능적인 요소를 함께 고려한 HAL 구조를 제안한다. 제안하는 HAL 구조의 효용성은 S3C2410 에서 실행하는 운영체제를 Cell BE 플랫폼으로 이식하는 사례 연구를 통해 검증하였다.

• Journal of Korea Multimedia Society
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• v.24 no.12
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• pp.1653-1662
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• 2021

In this paper, we propose a small waste appliance collection system that can be used for efficient waste appliance collection, and implement an unmanned automatic small waste appliance collector system. First, we collected cases related to the collection of waste home appliances, compared and analyzed methods, and arranged the characteristics. We analyzed at the requirements for the collection and management system of waste appliances by dividing it into the aspect of the discharger and the recycling business company. The collection system consists of a client-server structure, which is a collector system and a collection management server. The unmanned automatic collector system is divided into a control unit and a machine/mechanical unit. We identified the functions that the collector system must perform and the hardware required to perform these functions. Based on this, the collector system was implemented as an embedded system. The hardware and software used in the implementation are described and the implementation results are described. The collection system developed in this paper will contribute to the development of urban mining industry by enabling the efficient collection of waste appliances.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2020.06a
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• pp.117-118
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• 2020

The masonry structure is constructed by cement mortar binding material of brick objects and uses reinforced hardware (connected hardware or wall tie) together when building. However, over time, the corrosion of reinforced steel and the deterioration of joint mortar as well as bricks cause the risk of collapse. In particular, when the externally decorated brick wall is installed on the concrete girder for each floor, the angle bracket is not constructed or corroded, the full-layer weight load is applied to the wall of 0.5B, which is an example of full-scale or collapse. The purpose of this study is to provide numerical information on the reinforcement design by experimentally studying the structural performance of concrete reinforcement brackets that reinforce the vertical load of the exterior wall.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.328-335
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• 2010

In this paper, an efficient algorithm and area-efficient hardware architecture have been proposed for $2{\times}2$ MIMO-OFDM based WLAN baseband modem with two transmit and two receive antennas. To enhance the performance of the receiver, the efficient timing synchronization algorithm and symbol detector based on MML algorithm are presented. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate, the complexity of the proposed architecture is dramatically decreased. The proposed area-efficient hardware design was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. As a result, the complexity of the proposed modem receiver is reduced by 56% over the conventional architecture.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.263-272
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• 2005

The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).

• Journal of Korea Multimedia Society
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• v.15 no.10
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• pp.1247-1256
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• 2012

There are many filter based image processing algorithms and they usually require a huge amount of computations and memory accesses making it hard to attain a real-time performance, expecially in embedded applications. In this paper, we propose a pipelined hardware structure of the filter based face detection algorithm to show that the real time performance can be achieved by hardware design. In our design, the whole computation is divided into three pipeline stages: resizing the image (Resize), Transforming the image (ICT), and finding candidate area (Find Candidate). Each stage is optimized by considering the parallelism of the computation to reduce the number of cycles and utilizing the line memory to minimize the memory accesses. The resulting hardware uses 507 KB internal SRAM and occupies 9,039 LUTs when synthesized and configured on Xilinx Virtex5LX330 FPGA. It can operate at maximum 165MHz clock, giving the performance of 108 frame/sec, while detecting up to 20 faces.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.503-506
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• 2015

In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.439-446
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• 2011

In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz