• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1387-1391
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• 2003

The fundamental aim of this paper is to present a solution algorithm to achieve cooperative contour controlling, under joint acceleration constraint with maximum cooperative speed. Usually, the specifications like maximum velocity of cooperative trajectory are determined by the application itself. In resolving the cooperative trajectory into two complementary trajectories, an optimum task resolving strategy is employed so that the task assignment for each robot is fair under the joint acceleration constraint. The proposed algorithm of being an off-line technique, this could be effectively and conveniently extended to the existing servo control systems irrespective of the computational power of the controller implemented. Further, neither a change in hardware setup nor considerable reconfiguration of the existing system is required in adopting this technique. A simulation study has been carried out to verify that the proposed method can be realized in the generation of complementary trajectories so that they could meet the stipulated constraints in simultaneous maneuvering.

• Proceedings of the KSRS Conference
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• v.1
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• pp.271-273
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• 2006

In this paper, we describe the MI2U ORB function which is a part of the flight software executed on SCU and controls MI2U/MI which is one of three payloads on COMS. The MI2U ORB function manages MI2U/MI redundancy and reconfiguration, monitors MI2U/MI equipment, performs FDIR, and provides the routing service of commands from Ground/IP (Interpreted Program) through the current used 1553 channel. The MI2U hardware achieves the interface between the SCU and the MI. The MI2U is connected to SCU through MIL-STD-1553B system bus. The MI2U has the internal redundancy but is used in cold redundancy. The MI2U ORB function considers that they are not expected to be simultaneously switched on. The connection combination between MI2U and MI is electrically cross-strapped. However the MI2U ORB function considers only two combinations (MI2U A + MI 1, MI2U B + MI 2). Other combinations can be manually achieved by ground in case of the emergency case.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.277-286
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• 2000

Switch-based network is suitable for the environment of demanding high performance network. Traditional shared-medium Local Area Networks(LANs) do not provide sufficient throughput and latency. Specially, communication performance is more important with multimedia application. In these environments, switch-based network results in high performance. A kind of switch-based network provides higher bandwidth and low latency. Thus high-speed switch is essential to build switch-based LANs. An effective switch design is the most important factor of the switch-based network performance, and is required for the multicast message processing. In the previous cut-through switching technique, switch element reconfiguration has the capability of multicasting and deadlock-free. However, it has problems of low throughput as well as large scale of switch. Therfore, effective multicating can be implemented by using divided hardware unicast and multicast. The objective of this thesis is to suggest switch configuration with these features.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.674-680
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• 2008

An SDR (Software Defined Radio) system based on general purpose computing platform has benefits of ease of software development process, high degree of software compatibility, and cost-effectiveness of general purpose processors. This paper discusses design and implementation of a dual-mode SDR system that supports both cordless phone and walkie-talky system running on Linux-based general purpose computing platform. For this purpose, we designed modulation and demodulation software on open source-based GNU radio middleware. We also designed a customized RF front-end hardware which performs frequency conversion between RF and IF. The proposed SDR system successfully exhibited its ability to operate both cordless phone and walkie-talky communication on Intel processor-based general purpose computing platform. But experience with the prototype SDR system shows that further research is required for run-time software reconfiguration and efficient integration with conventional TCP/IP protocol stacks.

• Journal of the Korea Society for Simulation
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• v.19 no.1
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• pp.33-39
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• 2010

As future warfare becomes network-centric, war-game simulators require high interoperability between networked forces and dynamic reconfiguration in accordance with war events. In this paper, we propose an event-driven methodology to develop dynamic war-game simulations. Federates are developed by event-driven web services. The event-driven web services consistently sense war events and response them only if they are interested. By the sense-and-response mechanism and asynchronous event processing, we are able to save simulation time. An Anti-Surface-Warfare simulator is constructed to demonstrate the methodology and suggests that event-driven web services are efficient to model and simulate warfare where numerous events are generated from hardware systems and people dispersed on the network.

• Journal of Internet Computing and Services
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• v.13 no.6
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• pp.63-74
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• 2012

In this paper, we develop an integrated management/monitoring system that supports to dynamically reconfigure information models for systems or applications managed by heterogeneous distributed systems. When the subsystems on diverse platforms are added, removed, or modified, the altered configurations should conform to the configuration information of the integrated management/monitoring system. Further, upon the system configurations being changed, the altered system configurations should be synchronized with the information on the integrated management/monitoring system. Moreover, availability should be assured during synchronization to the extent that users can access the monitoring information with no system halting. This paper focuses on notifying the integrated management/monitoring system of any changes in hardware/software configurations on any subsystems under its management, and on dynamically re-configuring the information about hardware and software being managed based on the information notified. Finally, we expect that this research will be contributory to carrying out reliable integrated management by reflecting the information on any heterogeneous distributed systems in the integrated management/monitoring system.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}